ZXUNO DMA description

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mcleod_ideafix
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ZXUNO DMA description

Mensaje por mcleod_ideafix » 16 Abr 2020, 01:30

The DMA engine can do these types of transfer:
- Memory to memory (both using incrementing addresses)
- Memory to I/O (memory address incrementing)
- I/O to memory (memory address incrementing)
- I/O to I/O
I/O address is never changed during an I/O involved transfer.

The DMA module sits side by side with the Z80 CPU, so it "sees" the very same memory map that the Z80 sees. This means that DMA cannot transfer from or to memory that is not currently paged into the CPU address space.

It can operate in foreground, halting the main CPU during the transfer, or in the background, allowing the CPU to continue working (although a bit slower than usual).

DMA transfers can be burst transfers, in which data are transferred as fast as possible, normally halting the CPU in between, or timed, in which data is retrieved and transferred at a specified rate, controlled by an onchip timer. This last option is best suited for audio streaming directly from memory to a capable digital audio device, such a Specdrum or Covox (both integrated into the ZX-UNO)

Transfers can be retriggerable, or one shot. A retriggerable DMA transfer is the one that when it ends, it starts from the beginning again without software intervention. A one shot DMA transfer is that which ends and doesn't start over again unless software ditactes it so. Burst transfers can be only of type one shot. They cannot be retrigerable.

It's possible to know, for a non CPU halting DMA transfer, if certain source or destination address has been reached.

Currently, the DMA engine doesn't trigger any interrupt signal to the CPU.

I recommend reading the source code of dmaplayw . An ESXDOS command that streams a WAV file from SD to the Specdrum (I/O port $DF) device using DMA.
http://svn.zxuno.com/svn/zxuno/software/dma/dmaplayw

From the software point of view, the DMA engine is commanded by a group of registers. These are addressed and operated using two I/O ports from the ZXI address space:
$FC3B : register number to address
$FD3B : read or write to last addressed register. Note that the high order byte of this address is one more than the high order byte of the register number.

DMA register number to follow.

Código: Seleccionar todo

DMACTRL             equ 0a0h
DMASRC              equ 0a1h
DMADST              equ 0a2h
DMAPRE              equ 0a3h
DMALEN              equ 0a4h
DMAPROB             equ 0a5h
DMASTAT             equ 0a6h
Description of each register:

DMASRC :
Holds the source address in memory for a memory to memory transfer, or memory to I/O transfer.
Holds the I/O source address for a I/O to memory transfer, or I/O to I/O transfer.
16 bit R/W register (it needs two reads or two writes to transfer a 16 bit value from/to this register).
During and after a transfer, this register is not changed.

Example:

Código: Seleccionar todo

;Send 16 bit memory address in HL to DMASRC
ld bc,$FC3B  ;select register number
ld a,DMASRC  ;select DMASRC
out (c),a    ;do it
inc b        ;select register read/write
out (c),l    ;send LSB
out (c),h    ;send MSB
;Read it back into DE
in e,(c)     ;read LSB
in d,(c)     ;read MSB
DMADST :
Holds the destination address in memory for a memory to memory transfer, or memory to I/O transfer.
Holds the I/O destination address for a I/O to memory transfer, or I/O to I/O transfer.
16 bit R/W register (it needs two reads or two writes to transfer a 16 bit value from/to this register).
Example (see the DMASRC example)
During and after a transfer, this register is not changed.

DMALEN :
Holds the transfer byte length. 0 means 65536 bytes to transfer (need to check this though)
16 bit R/W register (it needs two reads or two writes to transfer a 16 bit value from/to this register).
Example (see the DMASRC example)
After a transfer, this register is not changed.

DMAPRE :
Holds a 16 bit preescaler value, which is used to determine the frequency rate for a timed transfer. The actual rate is determined by this formula:
Transfers per second = 28000000 / preescaler_value (for memory to memory transfers)
Transfers per second = 3500000 / preescaler_value (for transfers involving some sort of I/O address)
16 bit R/W register (it needs two reads or two writes to transfer a 16 bit value from/to this register).
Example (see the DMASRC example)
During and after a transfer, this register is not changed.

DMAPROB :
Holds a 16 bit value which identifies a memory address involved in a DMA transfer (it can be a source or destination address). When the DMA reads from (if configured as a source address) or writes to (if configured as a destination address) this memory address, bit 7 of DMASTAT is set.
16 bit R/W register (it needs two reads or two writes to transfer a 16 bit value from/to this register).
Example (see the DMASRC example)
During and after a transfer, this register is not changed.

DMASTAT :
8 bit status register. Currently, it uses only bit 7.
Bit 7: set to 1 when DMAPROB address has been reached. It automatically reset to 0 after reading this register.
8 bit, read only.

DMACTRL :
8 bit control register. Read/write. Reading it will give you the last written value. A DMA transfer is initiated from the "stop" condition, by writting any value other than 00 into the MODE bits. Stopping and initiating again a DMA transfer doesn't resume it. It starts from the beginning.
The bitfield description is this:
MODE : bits 1 and 0.
00 = DMA is stopped. The software can stop a timed DMA at any time writting 00 to these bits.
01 = burst DMA transfer. CPU is halted during the transfer. One shot.
10 = timed DMA transfer. One shot.
11 = timed DMA transfer, retriggerable.
DST : bit 2. 0 = destination address is memory. 1 = destination address is I/O
SRC : bit 3. 0 = source address is memory. 1 = source address is I/O
PROB: bit 4. 0 = address in DMAPROB is related to source (read) memory address. 1 = address in DMAPROB is related to destination (write) memory address.
Bits 5 to 7: Reserved. Written and read as 0.
http://www.zxuno.com
ZX-Uno · Clon de ordenador ZX Spectrum basado en FPGA

azesmbog
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Re: ZXUNO DMA description

Mensaje por azesmbog » 18 Abr 2020, 22:45

Лучше поздно, чем никогда?))

With the registers DMACTRL, DMASRC, DMADST, DMALEN and write to the port, I figured it out on my own.
With registers DMAPRE, DMAPROB, DMASTAT - from the description it became a little clearer than just from an example.
But I would like more examples using these registers.

Now the main and sad question.
Since there was only a single DMA Z80 for Spectrum computers, we naturally look at examples for it.
And the hedgehog understands that both the management and the functionality are completely different, but I would like to understand for myself how to replace certain teams, and is it possible at all.
A simple (or not very :) example. Command # 0D for DMA Z80
As I understand it, it does approximately the following:
# 0D - READ MASK (Port A Address Low, Byte Counter High, Status Byte)
Most likely used to synchronize and (or?) Suspend DMA.
Hence the question - how and how can I replace such a command in Uno DMA ??
Following the proverb - "It is better to see once than seven times - to hear" - I will give two pictures for an example:
reference image of multicolor in the emulator RealSpectrum
Imagen
and what could I achieve in Caesar's emulator
Imagen
I explain the problem - I need to synchronize every next DMA transaction with the beginning of the line.
In DMA Z80, this is apparently done by command 0D.
I just simply inserted a delay between transactions, although I understand that this is the worst solution.
So, is there a solution to my problem, or can I put a bold cross on this?

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mcleod_ideafix
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Re: ZXUNO DMA description

Mensaje por mcleod_ideafix » 20 Abr 2020, 04:20

azesmbog escribió:
18 Abr 2020, 22:45
Hence the question - how and how can I replace such a command in Uno DMA ??
ZX_UNO has line interrupt (aka raster interrupts). You can command the machine to do a INT on a specific scanline. You can then reprogram the raster interrupt to trigger an interrupt at the next line, and so on.

Anyway.... you know that the ZX-UNO implements Timex HiColour, so multicolor 8x1 attributes is already present in hardware.
http://www.zxuno.com
ZX-Uno · Clon de ordenador ZX Spectrum basado en FPGA

azesmbog
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Re: ZXUNO DMA description

Mensaje por azesmbog » 20 Abr 2020, 21:56

Мне было интересно изучить именно DMA в приложении к ZX Spectrum. C обычными режимами.
Не ULA+, ни Timex Hi-Color, ни Radastan Mode, ни блиттер и вершинные шейдеры.
Чисто ZX48 + DMA Uno в отличии от ZX48 +DMA Z80. И никаких 2068 и Chloe. Я ясно выражаюсь??
В любом случае, я что-то понял, что может (и чего не может) DMA. Для себя.
Да, я знаю, что вьювер MLT есть под timex-режимы, но мне хотелось его сделать классически, только с DMA.
Да, пришлось вставлять 8 циклов задержки, причем три из них различные, и долго-долго подбирать тайминги для мультиколора
И да, тайминги эмулятора Цезаря в отношении DMA совершенно ничего не имеют общего с реальными таймингами Uno, но все равно - без эмулятора я бы вообще ни в чем не разобрался.
В любом случае .... Спасибо!

azesmbog
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Registrado: 17 Feb 2016, 23:07

Часть I

Mensaje por azesmbog » 13 May 2020, 15:17

Чтобы закрыть для себя тему с DMA, выкладываю пак конверсионных работ.
Много тысячелетий назад люди делали, старались. но мало кто видел результат их титанической работы :)
Мне тоже пришлось немного постараться, дизассемблировав их программы, проанализировать работу с Z80 DMA, и собрать заново, но уже с Uno DMA.
И поправить тайминги. Вот почему два каталога, сперва поправил тайминги под ZX48, но потом решил, что все же основным является компьютер ZX128, поэтому поправил тайминги еще раз :) Так что запускать нужно в режиме Spectrum 128
Black1 & Black2 - viewer mlt-картинок, но просматривать лучше на ч\б экране телевизора, с выключенным цветом)
Color1 & Color2 - viewer цветных mlt-картинок. По нажатию Enter загружается следующая картинка.
DMA Demo 1,2,3 - демонстрационные программы, причем во второй и третьей можно жать различные цифровые клавиши.
Вообще то программирование надписей на бордюре - это высший пилотаж 80 lvl. Это все равно как писать вилами на воде.
To be continue...
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desUBIKado
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Re: ZXUNO DMA description

Mensaje por desUBIKado » 13 May 2020, 21:50

Entiendo que las imágenes, aunque tienen el aspecto de estar en Timex Hi-Color, realmente están hechas con interrupciones "raster", y pasado del sistema del DMA Z80 (¿es ese el que implementa el ZX Spectrum Next?) al DMA del ZX-Uno.

El resultado te ha quedado impecable.

La DMADEMO2 la he dejado hasta 2.000 bolas. El resultado es hipnotizante.

En la DMADEMO3 me ha gustado mucho los efectos de escritura en el borde superior, y sí, con las letras pequeñas no es tan fácil leer :D

azesmbog
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Re: ZXUNO DMA description

Mensaje por azesmbog » 13 May 2020, 22:00

desUBIKado escribió:
13 May 2020, 21:50
Entiendo que las imágenes, aunque tienen el aspecto de estar en Timex Hi-Color, realmente están hechas con interrupciones "raster", y pasado del sistema del DMA Z80 (¿es ese el que implementa el ZX Spectrum Next?) al DMA del ZX-Uno.
для Timex эта же программа была сделана для режима Hi-Color, но для обычного Spectrum она же была сделана с помощью DMA и на других принципах работы :)
в DMADEMO2 цифровыми клавишами можно менять траекторию фигур Лиссажу, а так же форму, и фон

azesmbog
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Часть III, пропущенная

Mensaje por azesmbog » 09 Ago 2020, 22:50

Так же, 2-3 месяца назад я сделал ядро с модулем zxnDMA вместо unoDMA.
Выкладываю его и в архиве все демонстрации, которые не надо переделывать, а можно прям брать с сайта Велесофт-а.
Некоторые особенности и отличия. этот модуль из ядра Следующего, но тут он подключен на порт 107, его и надо выбирать при запуске демо. У него два режима работы -первый, более менее приближенный к оригинальному z80DMA, и второй режим - zxnDMA - немного исправленный и модифицированный.
По умолчанию запускается режим z80DMA, но его в любой момент времени можно сменить на zxnDMA кнопкой HOME на клавиатуре. В некоторых демо даже улучшается картинка, например явно видно в multitech-color.

как бонус - MQM3 должна работать.

Ядро - в архиве.
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