desUBIKado escribió:Hola Fabio:
Una pregunta sobre MSX-DOS. ¿Es correcto que al poner MODE 41, MODE 42, ... MODE 80 devuelva el error *** Invalid parameter?
Si pongo un valor entre 1 y 40 funciona correctamente, y pone ese número de columnas por fila.
New MSX1 core
-
- Mensajes: 100
- Registrado: 08 Sep 2016, 13:10
Re: New MSX1 core
This core is a MSX1, VDP TMS9918, only 40 columns!
Re: New MSX1 core
Una preguntilla, he vuelto a poner la tele a 50hz y he configurado el config.txt y el core ahora arranca bien a 50hz, el problema es que cuando cargo una rom, nemesis2 en este caso me sale en blanco y negro. He probado con el core beta y sale todo en blanco y negro.
En la tele que soporta los 60hz con el config.txt en pal ningún problema.
Alguna solución, ¿quizá romload o loadrom tienen una opción para forzar 50hz?.
Saludos y gracias de antemano.
En la tele que soporta los 60hz con el config.txt en pal ningún problema.
Alguna solución, ¿quizá romload o loadrom tienen una opción para forzar 50hz?.
Saludos y gracias de antemano.
Re: New MSX1 core
Hello Fabio.fbelavenuto escribió:Source-code released:
https://github.com/fbelavenuto/msx1fpga
It's still in the beta stage!
First congratulations for your great work.
I am trying to synthesize version 3 from your GIT repository.
Through the script "_makeV3.cmd" I have the following output:
Código: Seleccionar todo
D:\msx1fpga-master\synth\zxuno>_makeV3.cmd
D:\msx1fpga-master\synth\zxuno>set ISEPATH=C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64
D:\msx1fpga-master\synth\zxuno>set MACHINE=zxuno_top
D:\msx1fpga-master\synth\zxuno>set UCFVERSION=v3
D:\msx1fpga-master\synth\zxuno>call C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\xst -intstyle ise -ifn zxuno_top.xst -ofn zxuno_top.syr
ERROR:Xst:438 - Can not open file : zxuno_top.prj
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.98 secs
-->
Total memory usage is 219296 kilobytes
Number of errors : 1 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
D:\msx1fpga-master\synth\zxuno>call C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc zxuno_pins_v3.ucf -p xc6slx9-tqg144- zxuno_top.ngc zxuno_top.ngd
ERROR:NgdBuild:653 - An invalid target package "tqg144-" was given in the "-p"
option value. Please consult the Xilinx Programmable Logic Data Book to find
a legal target package.
D:\msx1fpga-master\synth\zxuno>call C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\map -intstyle ise -w -ol high -mt 2 -p xc6slx9-tqg144- -logic_opt off -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -ir off -pr off -lc off -power off -o zxuno_top_map.ncd zxuno_top.ngd zxuno_top.pcf
ERROR:Map:92 - NGD file "zxuno_top.ngd" not found.
D:\msx1fpga-master\synth\zxuno>call C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\par -intstyle ise -w -ol high -mt 4 zxuno_top_map.ncd zxuno_top.ncd zxuno_top.pcf
ERROR:Par:73 - Cannot find Input file "zxuno_top_map.ncd". Please verify that your paths and permissions are properly
set for this file.
D:\msx1fpga-master\synth\zxuno>call C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\trce -intstyle ise -v 3 -s -n 3 -fastpaths -xml zxuno_top.twx zxuno_top.ncd -o zxuno_top.twr zxuno_top.pcf
ERROR:Portability:90 - Command line error: Argument <speed> must be specified
for the switch "-s".
Usage: trce.exe [-e|-v [<limit:0,2000000000>]] [-l <limit:0,2000000000>] [-n
[<limit:0,2000000000>]] [-u [<limit:0,2000000000>]] [-a] [-s <speed>] [-o
<report[.twr]>] [-stamp <stampfile>] [-tsi <tsifile[.tsi]>] [-xml
<report[.twx]>] [-nodatasheet] [-timegroups] [-fastpaths] [-noflight] [-intstyle
ise|xflow|silent] [-ise <projectfile>] [-filter <filter_file[.filter]>]
<design[.ncd]> [<constraint[.pcf]>]
<design[.ncd]> ... Xilinx physical design file (no default)
<constraint[.pcf]> ... optional physical constraint file (default design.pcf)
-o <report[.twr]> ... report output file (default design.twr)
-xml <report[.twx]> ... XML report output file (default design.twx)
-e [<limit>] ... produce detailed error report for timing constraints
optionally limited to the number of items specified by
<limit>
-v [<limit>] ... produce verbose timing report for timing constraints
optionally limited to the number of items specified by
<limit>
-l [<limit>] ... produce timing report for timing constraints
optionally limited to the number of items specified by
<limit>
-n [<limit>] ... report paths per endpoint (default is per constraint).
Limited to the number of endpoints specified by <limit>.
Worst value between setup and hold is used to identify
endpoint to report, using that endpoint for both setup
and hold details. Use -fastpaths, to report unique
endpoints for worst setup and worst hold. The -v <limit>
value, dictates the number of reported paths per
endpoint. This switch requries -v or -e
-s <speed> ... run analysis with the speed grade specified by <speed>.
This switch requries -v or -e
-a ... perform advanced design analysis in the absence
of a physical constraint file. This switch requires
-v or -e
-u [<limit>] ... report unconstrained paths optionally limited to the
number of items specified by <limit>. This switch
requries -v or -e
-f <filename> ... use the file specified by <filename> as command input
-stamp <stampfile> ... optionally generate STAMP model and data files. This
switch requires -v or -e
-tsi <tsifile[.tsi]> ... produce timing specification interaction report. This
switch requries -v or -e
-nodatasheet ... do not create the datasheet section of the report. This
switch requires -v or -e
-timegroups ... create the table of timegroups section of the report
This switch requires -v or -e
-fastpaths ... report fastest paths/verbose hold paths. This switch
requires -v or -e
-filter <filter_file[.filter] ... Message Filter file name (for example
"filter.filter"). If specified, the contents of this
file will be used to filter messages from this
application. The filter file can be created using
Xreport. This switch requires -v or -e
-noflight ... turn off the package flight delay
-intstyle <style> ... use the specified style: ise, xflow, or silent
-ise <projectfile> ... use the ISE project file specified by <projectfile>
TRCE: Creates a Timing Report file (TWR) derived from static timing
analysis of the Physical Design file (NCD). The analysis is typically
based on constraints included in the optional Physical Constraints
file (PCF).
D:\msx1fpga-master\synth\zxuno>call C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\bitgen -intstyle ise -f zxuno_top.ut zxuno_top.ncd
ERROR:Portability:37 - Unable to open command file "zxuno_top.ut". Please make
sure that this file exists and that you have read permission for it. This
message may also occur if you are currently having network problems.
D:\msx1fpga-master\synth\zxuno>pause
Presione una tecla para continuar . . .
I re-launched _makeV3.cmd and this time the process is longer but also ends in error:
Código: Seleccionar todo
D:\msx1fpga-master\synth\zxuno>_makeV3.cmd
D:\msx1fpga-master\synth\zxuno>set ISEPATH=C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64
D:\msx1fpga-master\synth\zxuno>set MACHINE=zxuno_top
D:\msx1fpga-master\synth\zxuno>set UCFVERSION=v3
D:\msx1fpga-master\synth\zxuno>call C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\xst -intstyle ise -ifn zxuno_top.xst -ofn zxuno_top.syr
Reading design: zxuno_top.prj
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "D:\msx1fpga-master\synth\zxuno\ipcore_dir\pll1.vhd" into library work
Parsing entity <pll1>.
Parsing architecture <xilinx> of entity <pll1>.
Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_pack-p.vhd" into library work
Parsing package <vdp18_pack>.
Parsing package body <vdp18_pack>.
Parsing VHDL file "D:\msx1fpga-master\src\ram\dpram.vhd" into library work
Parsing entity <dpram>.
Parsing architecture <rtl> of entity <dpram>.
Parsing VHDL file "D:\msx1fpga-master\src\cpu\t80_reg.vhd" into library work
Parsing entity <T80_Reg>.
Parsing architecture <rtl> of entity <t80_reg>.
Parsing VHDL file "D:\msx1fpga-master\src\cpu\t80_pack.vhd" into library work
Parsing package <T80_Pack>.
Parsing VHDL file "D:\msx1fpga-master\src\cpu\t80_mcode.vhd" into library work
Parsing entity <T80_MCode>.
Parsing architecture <rtl> of entity <t80_mcode>.
Parsing VHDL file "D:\msx1fpga-master\src\cpu\t80_alu.vhd" into library work
Parsing entity <T80_ALU>.
Parsing architecture <rtl> of entity <t80_alu>.
Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_sprite.vhd" into library work
Parsing entity <vdp18_sprite>.
Parsing architecture <rtl> of entity <vdp18_sprite>.
Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_pattern.vhd" into library work
Parsing entity <vdp18_pattern>.
Parsing architecture <rtl> of entity <vdp18_pattern>.
Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_palette.vhd" into library work
Parsing entity <vdp18_palette>.
Parsing architecture <Memory> of entity <vdp18_palette>.
Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_hor_vert.vhd" into library work
Parsing entity <vdp18_hor_vert>.
Parsing architecture <rtl> of entity <vdp18_hor_vert>.
Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_ctrl.vhd" into library work
Parsing entity <vdp18_ctrl>.
Parsing architecture <rtl> of entity <vdp18_ctrl>.
Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_cpuio.vhd" into library work
Parsing entity <vdp18_cpuio>.
Parsing architecture <rtl> of entity <vdp18_cpuio>.
Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_col_mux.vhd" into library work
Parsing entity <vdp18_col_mux>.
Parsing architecture <rtl> of entity <vdp18_col_mux>.
Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_clk_gen.vhd" into library work
Parsing entity <vdp18_clk_gen>.
Parsing architecture <rtl> of entity <vdp18_clk_gen>.
Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_addr_mux.vhd" into library work
Parsing entity <vdp18_addr_mux>.
Parsing architecture <rtl> of entity <vdp18_addr_mux>.
Parsing VHDL file "D:\msx1fpga-master\src\video\dblscan.vhd" into library work
Parsing entity <dblscan>.
Parsing architecture <rtl> of entity <dblscan>.
Parsing VHDL file "D:\msx1fpga-master\src\peripheral\escci\scc_wave.vhd" into library work
Parsing entity <scc_wave_mul>.
Parsing architecture <rtl> of entity <scc_wave_mul>.
Parsing entity <scc_wave>.
Parsing architecture <Behavior> of entity <scc_wave>.
Parsing VHDL file "D:\msx1fpga-master\src\cpu\t80.vhd" into library work
Parsing entity <T80>.
Parsing architecture <rtl> of entity <t80>.
Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_core.vhd" into library work
Parsing entity <vdp18_core>.
Parsing architecture <struct> of entity <vdp18_core>.
Parsing VHDL file "D:\msx1fpga-master\src\rom\ipl_rom.vhd" into library work
Parsing entity <ipl_rom>.
Parsing architecture <rtl> of entity <ipl_rom>.
Parsing VHDL file "D:\msx1fpga-master\src\peripheral\swioports.vhd" into library work
Parsing entity <swioports>.
Parsing architecture <Behavior> of entity <swioports>.
Parsing VHDL file "D:\msx1fpga-master\src\peripheral\spi.vhd" into library work
Parsing entity <spi>.
Parsing architecture <rtl> of entity <spi>.
Parsing VHDL file "D:\msx1fpga-master\src\peripheral\romnextor.vhd" into library work
Parsing entity <romnextor>.
Parsing architecture <Behavior> of entity <romnextor>.
Parsing VHDL file "D:\msx1fpga-master\src\peripheral\ps2_iobase.vhd" into library work
Parsing entity <ps2_iobase>.
Parsing architecture <rtl> of entity <ps2_iobase>.
Parsing VHDL file "D:\msx1fpga-master\src\peripheral\pio.vhd" into library work
Parsing entity <PIO>.
Parsing architecture <Behavior> of entity <pio>.
Parsing VHDL file "D:\msx1fpga-master\src\peripheral\keymap.vhd" into library work
Parsing entity <keymap>.
Parsing architecture <RTL> of entity <keymap>.
Parsing VHDL file "D:\msx1fpga-master\src\peripheral\exp_slot.vhd" into library work
Parsing entity <exp_slot>.
Parsing architecture <rtl> of entity <exp_slot>.
Parsing VHDL file "D:\msx1fpga-master\src\peripheral\escci\escci.vhd" into library work
Parsing entity <escci>.
Parsing architecture <Behavior> of entity <escci>.
Parsing VHDL file "D:\msx1fpga-master\src\cpu\t80a.vhd" into library work
Parsing entity <T80a>.
Parsing architecture <rtl> of entity <t80a>.
Parsing VHDL file "D:\msx1fpga-master\src\audio\YM2149.vhd" into library work
Parsing entity <YM2149>.
Parsing architecture <RTL> of entity <ym2149>.
Parsing VHDL file "D:\msx1fpga-master\src\audio\dac.vhd" into library work
Parsing entity <dac>.
Parsing architecture <rtl> of entity <dac>.
Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_paletas_3bit_pack.vhd" into library work
Parsing package <vdp18_paletas_3bit_pack>.
Parsing VHDL file "D:\msx1fpga-master\src\shared\multiboot.vhd" into library work
Parsing entity <multiboot>.
Parsing architecture <Behavioral> of entity <multiboot>.
Parsing VHDL file "D:\msx1fpga-master\src\rom\mainrom.vhd" into library work
Parsing entity <mainrom>.
Parsing architecture <rtl> of entity <mainrom>.
Parsing VHDL file "D:\msx1fpga-master\src\ram\spram.vhd" into library work
Parsing entity <spram>.
Parsing architecture <rtl> of entity <spram>.
Parsing VHDL file "D:\msx1fpga-master\src\peripheral\keyboard.vhd" into library work
Parsing entity <keyboard>.
Parsing architecture <Behavior> of entity <keyboard>.
Parsing VHDL file "D:\msx1fpga-master\src\msx.vhd" into library work
Parsing entity <msx>.
Parsing architecture <Behavior> of entity <msx>.
Parsing VHDL file "D:\msx1fpga-master\src\clocks.vhd" into library work
Parsing entity <clocks>.
Parsing architecture <rtl> of entity <clocks>.
Parsing VHDL file "D:\msx1fpga-master\src\audio\Audio_DAC.vhd" into library work
Parsing entity <Audio_DAC>.
Parsing architecture <Behavior> of entity <audio_dac>.
Parsing VHDL file "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" into library work
Parsing entity <zxuno_top>.
Parsing architecture <behavior> of entity <zxuno_top>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating entity <zxuno_top> (architecture <behavior>) from library <work>.
Elaborating entity <pll1> (architecture <xilinx>) from library <work>.
Elaborating entity <clocks> (architecture <rtl>) from library <work>.
Elaborating entity <msx> (architecture <Behavior>) with generics from library <work>.
Elaborating entity <T80a> (architecture <rtl>) with generics from library <work>.
Elaborating entity <T80> (architecture <rtl>) with generics from library <work>.
Elaborating entity <T80_MCode> (architecture <rtl>) with generics from library <work>.
Elaborating entity <T80_ALU> (architecture <rtl>) with generics from library <work>.
Elaborating entity <T80_Reg> (architecture <rtl>) from library <work>.
Elaborating entity <ipl_rom> (architecture <rtl>) from library <work>.
Elaborating entity <vdp18_core> (architecture <struct>) with generics from library <work>.
INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_pack-p.vhd" Line 217. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_pack-p.vhd" Line 217. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_pack-p.vhd" Line 217. Case statement is complete. others clause is never selected
Elaborating entity <vdp18_clk_gen> (architecture <rtl>) from library <work>.
Elaborating entity <vdp18_hor_vert> (architecture <rtl>) from library <work>.
Elaborating entity <vdp18_ctrl> (architecture <rtl>) from library <work>.
INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_ctrl.vhd" Line 251. Case statement is complete. others clause is never selected
Elaborating entity <vdp18_cpuio> (architecture <rtl>) from library <work>.
INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_cpuio.vhd" Line 518. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_cpuio.vhd" Line 564. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_pack-p.vhd" Line 217. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_pack-p.vhd" Line 217. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_pack-p.vhd" Line 217. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_pack-p.vhd" Line 217. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_pack-p.vhd" Line 217. Case statement is complete. others clause is never selected
Elaborating entity <vdp18_addr_mux> (architecture <rtl>) from library <work>.
INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_addr_mux.vhd" Line 169. Case statement is complete. others clause is never selected
Elaborating entity <vdp18_pattern> (architecture <rtl>) from library <work>.
INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_pattern.vhd" Line 218. Case statement is complete. others clause is never selected
Elaborating entity <vdp18_sprite> (architecture <rtl>) from library <work>.
Elaborating entity <vdp18_col_mux> (architecture <rtl>) from library <work>.
Elaborating entity <vdp18_palette> (architecture <Memory>) from library <work>.
Elaborating entity <dblscan> (architecture <rtl>) from library <work>.
Elaborating entity <dpram> (architecture <rtl>) with generics from library <work>.
Elaborating entity <YM2149> (architecture <RTL>) from library <work>.
INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\audio\YM2149.vhd" Line 177. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\audio\YM2149.vhd" Line 215. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\audio\YM2149.vhd" Line 254. Case statement is complete. others clause is never selected
Elaborating entity <PIO> (architecture <Behavior>) from library <work>.
Elaborating entity <exp_slot> (architecture <rtl>) from library <work>.
Elaborating entity <swioports> (architecture <Behavior>) from library <work>.
Elaborating entity <spi> (architecture <rtl>) from library <work>.
Elaborating entity <romnextor> (architecture <Behavior>) from library <work>.
Elaborating entity <escci> (architecture <Behavior>) from library <work>.
Elaborating entity <scc_wave> (architecture <Behavior>) from library <work>.
Elaborating entity <dpram> (architecture <rtl>) with generics from library <work>.
Elaborating entity <scc_wave_mul> (architecture <rtl>) from library <work>.
Elaborating entity <mainrom> (architecture <rtl>) from library <work>.
Elaborating entity <keyboard> (architecture <Behavior>) from library <work>.
Elaborating entity <ps2_iobase> (architecture <rtl>) from library <work>.
Elaborating entity <keymap> (architecture <RTL>) from library <work>.
Elaborating entity <Audio_DAC> (architecture <Behavior>) from library <work>.
Elaborating entity <dac> (architecture <rtl>) with generics from library <work>.
Elaborating entity <spram> (architecture <rtl>) with generics from library <work>.
Elaborating entity <multiboot> (architecture <Behavioral>) from library <work>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <zxuno_top>.
Related source file is "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd".
WARNING:Xst:647 - Input <flash_miso_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 192: Output port <clock_5m_en_o> of the instance <clks> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <bus_addr_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <bus_data_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <cnt_hor_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <cnt_ver_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <D_slots_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <ram_ce_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <ram_oe_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <rom_ce_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <rom_oe_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <bus_rd_n_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <bus_wr_n_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <bus_m1_n_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <bus_iorq_n_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <bus_mreq_n_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <bus_sltsl1_n_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <bus_sltsl2_n_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <vram_ce_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <vram_oe_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <caps_en_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <k7_motor_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <k7_audio_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <joy2_out_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <ntsc_pal_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <D_wait_o> of the instance <the_msx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 345: Output port <audio_mix_o> of the instance <audio> is unconnected or connected to loadless signal.
WARNING:Xst:2935 - Signal 'flash_cs_n_o', unconnected in block 'zxuno_top', is tied to its initial value (1).
WARNING:Xst:2935 - Signal 'flash_sclk_o', unconnected in block 'zxuno_top', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'flash_mosi_o', unconnected in block 'zxuno_top', is tied to its initial value (0).
Found 8-bit register for signal <por_cnt_s>.
Found 8-bit register for signal <soft_rst_cnt_s>.
Found 8-bit subtractor for signal <GND_5_o_GND_5_o_sub_2_OUT<7:0>> created at line 1308.
Found 8-bit subtractor for signal <GND_5_o_GND_5_o_sub_9_OUT<7:0>> created at line 1308.
Found 1-bit tristate buffer for signal <sram_data_io<7>> created at line 412
Found 1-bit tristate buffer for signal <sram_data_io<6>> created at line 412
Found 1-bit tristate buffer for signal <sram_data_io<5>> created at line 412
Found 1-bit tristate buffer for signal <sram_data_io<4>> created at line 412
Found 1-bit tristate buffer for signal <sram_data_io<3>> created at line 412
Found 1-bit tristate buffer for signal <sram_data_io<2>> created at line 412
Found 1-bit tristate buffer for signal <sram_data_io<1>> created at line 412
Found 1-bit tristate buffer for signal <sram_data_io<0>> created at line 412
Summary:
inferred 2 Adder/Subtractor(s).
inferred 16 D-type flip-flop(s).
inferred 2 Multiplexer(s).
inferred 8 Tristate(s).
Unit <zxuno_top> synthesized.
Synthesizing Unit <pll1>.
Related source file is "D:\msx1fpga-master\synth\zxuno\ipcore_dir\pll1.vhd".
Summary:
no macro.
Unit <pll1> synthesized.
Synthesizing Unit <clocks>.
Related source file is "D:\msx1fpga-master\src\clocks.vhd".
Found 3-bit register for signal <clk1_cnt_q>.
Found 3-bit register for signal <clk2_cnt_q>.
Found 2-bit register for signal <pos_cnt3_q>.
Found 2-bit register for signal <neg_cnt3_q>.
Found 2-bit register for signal <sw_ff_q>.
Found 1-bit register for signal <clock_5m_en_s>.
Found 1-bit register for signal <clock_vdp_s>.
Found 1-bit register for signal <clock_3m_s>.
Found 1-bit register for signal <clock_psg_en_s>.
Found 2-bit adder for signal <pos_cnt3_q[1]_GND_11_o_add_12_OUT> created at line 1241.
Found 2-bit adder for signal <neg_cnt3_q[1]_GND_11_o_add_17_OUT> created at line 1241.
Found 3-bit subtractor for signal <GND_11_o_GND_11_o_sub_2_OUT<2:0>> created at line 1308.
Found 3-bit subtractor for signal <GND_11_o_GND_11_o_sub_8_OUT<2:0>> created at line 1308.
Found 1-bit 4-to-1 multiplexer for signal <clock_cpu_o> created at line 164.
Summary:
inferred 4 Adder/Subtractor(s).
inferred 16 D-type flip-flop(s).
inferred 6 Multiplexer(s).
Unit <clocks> synthesized.
Synthesizing Unit <msx>.
Related source file is "D:\msx1fpga-master\src\msx.vhd".
hw_id_g = 8
hw_txt_g = "ZX-Uno Board"
hw_version_g = "00010001"
video_opt_g = 1
INFO:Xst:3210 - "D:\msx1fpga-master\src\msx.vhd" line 277: Output port <halt_n_o> of the instance <cpu> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\msx.vhd" line 277: Output port <busak_n_o> of the instance <cpu> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\msx.vhd" line 345: Output port <port_a_o> of the instance <psg> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\msx.vhd" line 345: Output port <audio_ch_a_o> of the instance <psg> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\msx.vhd" line 345: Output port <audio_ch_b_o> of the instance <psg> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\msx.vhd" line 345: Output port <audio_ch_c_o> of the instance <psg> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\msx.vhd" line 474: Output port <ram_oe_o> of the instance <escci> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\msx.vhd" line 474: Output port <ram_we_o> of the instance <escci> is unconnected or connected to loadless signal.
Found 5-bit register for signal <ram_page_s>.
Found 3-bit register for signal <mp_bank0_s>.
Found 3-bit register for signal <mp_bank1_s>.
Found 3-bit register for signal <mp_bank2_s>.
Found 3-bit register for signal <mp_bank3_s>.
Found 2-bit register for signal <m1_wait_ff_s>.
Found 1-bit register for signal <iplram_bw_s>.
Found 2-bit 4-to-1 multiplexer for signal <pslot_s> created at line 587.
Found 8-bit 4-to-1 multiplexer for signal <d_from_mp_s> created at line 218.
Found 3-bit 4-to-1 multiplexer for signal <mp_page_s> created at line 212.
Found 1-bit tristate buffer for signal <joy1_btn1_io> created at line 518
Found 1-bit tristate buffer for signal <joy1_btn2_io> created at line 519
Found 1-bit tristate buffer for signal <joy2_btn1_io> created at line 520
Found 1-bit tristate buffer for signal <joy2_btn2_io> created at line 521
Summary:
inferred 20 D-type flip-flop(s).
inferred 24 Multiplexer(s).
inferred 4 Tristate(s).
Unit <msx> synthesized.
Synthesizing Unit <T80a>.
Related source file is "D:\msx1fpga-master\src\cpu\t80a.vhd".
mode_g = 0
INFO:Xst:3210 - "D:\msx1fpga-master\src\cpu\t80a.vhd" line 152: Output port <IntE> of the instance <u0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\cpu\t80a.vhd" line 152: Output port <Stop> of the instance <u0> is unconnected or connected to loadless signal.
Found 1-bit register for signal <iorq_n_s>.
Found 1-bit register for signal <wr_n_s>.
Found 1-bit register for signal <reset_s>.
Found 1-bit register for signal <req_inhibit_s>.
Found 1-bit register for signal <mreq_inhibit_s>.
Found 1-bit register for signal <rd_s>.
Found 1-bit register for signal <mreq_s>.
Found 1-bit register for signal <wait_s>.
Found 8-bit register for signal <data_r>.
Found 1-bit register for signal <ireq_inhibit_n_s>.
Found 1-bit tristate buffer for signal <mreq_n_o> created at line 135
Found 1-bit tristate buffer for signal <iorq_n_o> created at line 136
Found 1-bit tristate buffer for signal <rd_n_o> created at line 137
Found 1-bit tristate buffer for signal <wr_n_o> created at line 138
Found 1-bit tristate buffer for signal <refresh_n_o> created at line 139
Found 1-bit tristate buffer for signal <address_o<15>> created at line 140
Found 1-bit tristate buffer for signal <address_o<14>> created at line 140
Found 1-bit tristate buffer for signal <address_o<13>> created at line 140
Found 1-bit tristate buffer for signal <address_o<12>> created at line 140
Found 1-bit tristate buffer for signal <address_o<11>> created at line 140
Found 1-bit tristate buffer for signal <address_o<10>> created at line 140
Found 1-bit tristate buffer for signal <address_o<9>> created at line 140
Found 1-bit tristate buffer for signal <address_o<8>> created at line 140
Found 1-bit tristate buffer for signal <address_o<7>> created at line 140
Found 1-bit tristate buffer for signal <address_o<6>> created at line 140
Found 1-bit tristate buffer for signal <address_o<5>> created at line 140
Found 1-bit tristate buffer for signal <address_o<4>> created at line 140
Found 1-bit tristate buffer for signal <address_o<3>> created at line 140
Found 1-bit tristate buffer for signal <address_o<2>> created at line 140
Found 1-bit tristate buffer for signal <address_o<1>> created at line 140
Found 1-bit tristate buffer for signal <address_o<0>> created at line 140
Summary:
inferred 17 D-type flip-flop(s).
inferred 13 Multiplexer(s).
inferred 21 Tristate(s).
Unit <T80a> synthesized.
Synthesizing Unit <T80>.
Related source file is "D:\msx1fpga-master\src\cpu\t80.vhd".
Mode = 0
IOWait = 1
Flag_C = 0
Flag_N = 1
Flag_P = 2
Flag_X = 3
Flag_H = 4
Flag_Y = 5
Flag_Z = 6
Flag_S = 7
Found 1-bit register for signal <RFSH_n>.
Found 1-bit register for signal <M1_n>.
Found 1-bit register for signal <Alternate>.
Found 1-bit register for signal <Arith16_r>.
Found 1-bit register for signal <BTR_r>.
Found 1-bit register for signal <Z16_r>.
Found 1-bit register for signal <ALU_cpi_r>.
Found 1-bit register for signal <Save_ALU_r>.
Found 1-bit register for signal <PreserveC_r>.
Found 1-bit register for signal <XY_Ind>.
Found 1-bit register for signal <INT_s>.
Found 1-bit register for signal <NMI_s>.
Found 1-bit register for signal <Halt_FF>.
Found 1-bit register for signal <NMICycle>.
Found 1-bit register for signal <IntCycle>.
Found 1-bit register for signal <IntE_FF1>.
Found 1-bit register for signal <IntE_FF2>.
Found 1-bit register for signal <No_BTR>.
Found 1-bit register for signal <Auto_Wait_t1>.
Found 1-bit register for signal <Auto_Wait_t2>.
Found 16-bit register for signal <SP>.
Found 8-bit register for signal <F>.
Found 8-bit register for signal <Ap>.
Found 8-bit register for signal <Fp>.
Found 8-bit register for signal <ACC>.
Found 16-bit register for signal <A>.
Found 16-bit register for signal <TmpAddr>.
Found 16-bit register for signal <PC>.
Found 8-bit register for signal <IR>.
Found 8-bit register for signal <DO>.
Found 8-bit register for signal <I>.
Found 8-bit register for signal <R>.
Found 2-bit register for signal <ISet>.
Found 2-bit register for signal <XY_State>.
Found 2-bit register for signal <IStatus>.
Found 3-bit register for signal <MCycles>.
Found 3-bit register for signal <TState>.
Found 3-bit register for signal <Pre_XY_F_M>.
Found 5-bit register for signal <Read_To_Reg_r>.
Found 4-bit register for signal <ALU_Op_r>.
Found 3-bit register for signal <MCycle>.
Found 3-bit register for signal <RegAddrA_r>.
Found 3-bit register for signal <RegAddrB_r>.
Found 3-bit register for signal <RegAddrC>.
Found 1-bit register for signal <IncDecZ>.
Found 16-bit register for signal <RegBusA_r>.
Found 8-bit register for signal <BusB>.
Found 8-bit register for signal <BusA>.
Found 7-bit adder for signal <R[6]_GND_36_o_add_15_OUT> created at line 1241.
Found 16-bit adder for signal <TmpAddr[15]_GND_36_o_add_46_OUT> created at line 1241.
Found 16-bit adder for signal <PC[15]_DI_Reg[7]_add_69_OUT> created at line 568.
Found 16-bit adder for signal <PC[15]_GND_36_o_add_70_OUT> created at line 1241.
Found 16-bit adder for signal <RegBusC[15]_DI_Reg[7]_add_81_OUT> created at line 581.
Found 16-bit adder for signal <SP[15]_GND_36_o_add_88_OUT> created at line 1241.
Found 16-bit adder for signal <RegBusA[15]_GND_36_o_add_215_OUT> created at line 1253.
Found 3-bit adder for signal <Pre_XY_F_M[2]_GND_36_o_add_268_OUT> created at line 1241.
Found 3-bit adder for signal <MCycle[2]_GND_36_o_add_273_OUT> created at line 1241.
Found 3-bit adder for signal <TState[2]_GND_36_o_add_281_OUT> created at line 1241.
Found 16-bit subtractor for signal <GND_36_o_GND_36_o_sub_74_OUT<15:0>> created at line 1308.
Found 16-bit subtractor for signal <GND_36_o_GND_36_o_sub_88_OUT<15:0>> created at line 1308.
Found 16-bit subtractor for signal <RegBusA[15]_GND_36_o_sub_217_OUT<15:0>> created at line 1320.
Found 16-bit 7-to-1 multiplexer for signal <Set_Addr_To[2]_PC[15]_wide_mux_48_OUT> created at line 487.
Found 8-bit 3-to-1 multiplexer for signal <Special_LD[1]_ACC[7]_wide_mux_110_OUT> created at line 617.
Found 8-bit 11-to-1 multiplexer for signal <Set_BusB_To[3]_X_35_o_wide_mux_243_OUT> created at line 863.
Found 8-bit 3-to-1 multiplexer for signal <_n1475> created at line 617.
Found 3-bit comparator equal for signal <T_Res> created at line 345
Found 3-bit comparator equal for signal <MCycles[2]_MCycle[2]_equal_270_o> created at line 1051
WARNING:Xst:2404 - FFs/Latches <BusReq_s<0:0>> (without init value) have a constant value of 0 in block <T80>.
WARNING:Xst:2404 - FFs/Latches <BusAck<0:0>> (without init value) have a constant value of 0 in block <T80>.
Summary:
inferred 10 Adder/Subtractor(s).
inferred 215 D-type flip-flop(s).
inferred 2 Comparator(s).
inferred 236 Multiplexer(s).
Unit <T80> synthesized.
Synthesizing Unit <T80_MCode>.
Related source file is "D:\msx1fpga-master\src\cpu\t80_mcode.vhd".
Mode = 0
Flag_C = 0
Flag_N = 1
Flag_P = 2
Flag_X = 3
Flag_H = 4
Flag_Y = 5
Flag_Z = 6
Flag_S = 7
WARNING:Xst:647 - Input <F<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <F<5:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 1-bit 8-to-1 multiplexer for signal <IR[5]_F[7]_Mux_192_o> created at line 174.
Found 4-bit 3-to-1 multiplexer for signal <ISet[1]_IR[7]_wide_mux_506_OUT> created at line 253.
Found 4-bit 3-to-1 multiplexer for signal <Set_BusA_To> created at line 253.
Found 1-bit 3-to-1 multiplexer for signal <Read_To_Reg> created at line 253.
Found 3-bit 3-to-1 multiplexer for signal <MCycles> created at line 253.
Found 1-bit 3-to-1 multiplexer for signal <ISet[1]_IR[7]_Mux_511_o> created at line 253.
Found 3-bit 3-to-1 multiplexer for signal <ISet[1]_IR[7]_wide_mux_512_OUT> created at line 253.
Found 1-bit 3-to-1 multiplexer for signal <Write> created at line 253.
Found 1-bit 3-to-1 multiplexer for signal <Read_To_Acc> created at line 253.
Found 1-bit 3-to-1 multiplexer for signal <LDZ> created at line 253.
Found 1-bit 3-to-1 multiplexer for signal <LDW> created at line 253.
Found 1-bit 3-to-1 multiplexer for signal <Inc_WZ> created at line 253.
Found 3-bit 3-to-1 multiplexer for signal <ISet[1]_IR[7]_wide_mux_518_OUT> created at line 253.
Found 4-bit 3-to-1 multiplexer for signal <IncDec_16> created at line 253.
Found 1-bit 3-to-1 multiplexer for signal <Save_ALU> created at line 253.
Found 1-bit 3-to-1 multiplexer for signal <PreserveC> created at line 253.
Found 4-bit 3-to-1 multiplexer for signal <ALU_Op> created at line 253.
Found 1-bit 3-to-1 multiplexer for signal <Jump> created at line 253.
Found 1-bit 3-to-1 multiplexer for signal <ISet[1]_IR[7]_Mux_534_o> created at line 253.
Found 1-bit 3-to-1 multiplexer for signal <IORQ> created at line 253.
Summary:
inferred 400 Multiplexer(s).
Unit <T80_MCode> synthesized.
Synthesizing Unit <T80_ALU>.
Related source file is "D:\msx1fpga-master\src\cpu\t80_alu.vhd".
Mode = 0
Flag_C = 0
Flag_N = 1
Flag_P = 2
Flag_X = 3
Flag_H = 4
Flag_Y = 5
Flag_Z = 6
Flag_S = 7
Found 6-bit adder for signal <n0127> created at line 107.
Found 5-bit adder for signal <n0126> created at line 107.
Found 3-bit adder for signal <n0125> created at line 107.
Found 6-bit adder for signal <n0128> created at line 107.
Found 9-bit adder for signal <GND_38_o_GND_38_o_add_23_OUT> created at line 1241.
Found 9-bit adder for signal <GND_38_o_GND_38_o_add_26_OUT> created at line 1241.
Found 8-bit subtractor for signal <GND_38_o_GND_38_o_sub_31_OUT<7:0>> created at line 1308.
Found 9-bit subtractor for signal <GND_38_o_GND_38_o_sub_34_OUT<8:0>> created at line 1308.
Found 8-bit 8-to-1 multiplexer for signal <IR[5]_GND_38_o_wide_mux_44_OUT> created at line 299.
Found 5-bit comparator greater for signal <GND_38_o_GND_38_o_LessThan_26_o> created at line 225
Found 4-bit comparator greater for signal <PWR_17_o_BusA[3]_LessThan_29_o> created at line 230
Found 4-bit comparator greater for signal <GND_38_o_BusA[3]_LessThan_30_o> created at line 231
Found 8-bit comparator greater for signal <PWR_17_o_BusA[7]_LessThan_33_o> created at line 236
Summary:
inferred 8 Adder/Subtractor(s).
inferred 4 Comparator(s).
inferred 59 Multiplexer(s).
Unit <T80_ALU> synthesized.
Synthesizing Unit <T80_Reg>.
Related source file is "D:\msx1fpga-master\src\cpu\t80_reg.vhd".
Found 8x8-bit dual-port RAM <Mram_RegsH> for signal <RegsH>.
Found 8x8-bit dual-port RAM <Mram_RegsL> for signal <RegsL>.
Summary:
inferred 4 RAM(s).
Unit <T80_Reg> synthesized.
Synthesizing Unit <ipl_rom>.
Related source file is "D:\msx1fpga-master\src\rom\ipl_rom.vhd".
Found 8-bit register for signal <data>.
Found 8192x8-bit Read Only RAM for signal <addr[12]_PWR_24_o_wide_mux_0_OUT>
Summary:
inferred 1 RAM(s).
inferred 8 D-type flip-flop(s).
Unit <ipl_rom> synthesized.
Synthesizing Unit <vdp18_core>.
Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_core.vhd".
video_opt_g = 1
INFO:Xst:3210 - "D:\msx1fpga-master\src\video\vdp18\vdp18_core.vhd" line 204: Output port <clk_en_3m58_o> of the instance <clk_gen_b> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\video\vdp18\vdp18_core.vhd" line 204: Output port <clk_en_2m68_o> of the instance <clk_gen_b> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\video\vdp18\vdp18_core.vhd" line 264: Output port <cd_oe_o> of the instance <cpu_io_b> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\video\vdp18\vdp18_core.vhd" line 264: Output port <reg_ev_o> of the instance <cpu_io_b> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\video\vdp18\vdp18_core.vhd" line 264: Output port <reg_16k_o> of the instance <cpu_io_b> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\video\vdp18\vdp18_core.vhd" line 466: Output port <oddline_o> of the instance <vo1_2.scandbl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\video\vdp18\vdp18_core.vhd" line 466: Output port <hblank_o> of the instance <vo1_2.scandbl> is unconnected or connected to loadless signal.
Found 4-bit register for signal <rgb_g_o>.
Found 4-bit register for signal <rgb_b_o>.
Found 4-bit register for signal <rgb_r_o>.
Summary:
inferred 12 D-type flip-flop(s).
inferred 3 Multiplexer(s).
Unit <vdp18_core> synthesized.
Synthesizing Unit <vdp18_clk_gen>.
Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_clk_gen.vhd".
Found 4-bit register for signal <cnt_q>.
Found 4-bit adder for signal <cnt_q[3]_GND_45_o_add_1_OUT> created at line 1241.
Found 8x1-bit Read Only RAM for signal <cnt_q[3]_GND_45_o_Mux_5_o>
Found 16x2-bit Read Only RAM for signal <_n0036>
Summary:
inferred 2 RAM(s).
inferred 1 Adder/Subtractor(s).
inferred 4 D-type flip-flop(s).
inferred 4 Multiplexer(s).
Unit <vdp18_clk_gen> synthesized.
Synthesizing Unit <vdp18_hor_vert>.
Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_hor_vert.vhd".
Found 1-bit register for signal <hsync_n_o>.
Found 1-bit register for signal <vsync_n_o>.
Found 9-bit register for signal <cnt_hor_s>.
Found 8-bit register for signal <cnt_ver_s>.
Found 9-bit register for signal <cnt_hor_q>.
Found 1-bit register for signal <hblank_q>.
Found 1-bit register for signal <vblank_q>.
Found 1-bit register for signal <cnt_vert_q<8>>.
Found 1-bit register for signal <cnt_vert_q<7>>.
Found 1-bit register for signal <cnt_vert_q<6>>.
Found 1-bit register for signal <cnt_vert_q<5>>.
Found 1-bit register for signal <cnt_vert_q<4>>.
Found 1-bit register for signal <cnt_vert_q<3>>.
Found 1-bit register for signal <cnt_vert_q<2>>.
Found 1-bit register for signal <cnt_vert_q<1>>.
Found 1-bit register for signal <cnt_vert_q<0>>.
Found 9-bit adder for signal <cnt_hor_q[0]_GND_46_o_add_6_OUT> created at line 1253.
Found 9-bit adder for signal <cnt_vert_q[0]_GND_46_o_add_9_OUT> created at line 1253.
Found 9-bit adder for signal <first_line_s[0]_GND_46_o_add_24_OUT> created at line 1253.
Found 9-bit adder for signal <cnt_hor_s[8]_GND_46_o_add_34_OUT> created at line 1241.
Found 8-bit adder for signal <cnt_ver_s[7]_GND_46_o_add_37_OUT> created at line 1241.
Found 9-bit comparator equal for signal <cnt_hor_q[0]_last_pix_s[0]_equal_6_o> created at line 146
Found 9-bit comparator equal for signal <cnt_vert_q[0]_last_line_s[0]_equal_9_o> created at line 153
Found 9-bit comparator not equal for signal <cnt_vert_q[0]_first_line_s[0]_equal_26_o> created at line 194
Summary:
inferred 5 Adder/Subtractor(s).
inferred 39 D-type flip-flop(s).
inferred 3 Comparator(s).
inferred 8 Multiplexer(s).
Unit <vdp18_hor_vert> synthesized.
Synthesizing Unit <vdp18_ctrl>.
Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_ctrl.vhd".
Found 1-bit register for signal <sprite_active_q>.
Found 1-bit register for signal <sprite_line_act_q>.
Found 1-bit register for signal <hor_active_q>.
Found 1-bit register for signal <vert_active_q>.
Found 1-bit register for signal <vram_ce_o>.
Found 1-bit register for signal <vram_oe_o>.
Found 1-bit register for signal <vram_ctrl.read_b_v>.
Found 9-bit adder for signal <decode_access.num_pix_plus_6_v> created at line 1253.
Found 9-bit adder for signal <n0643> created at line 1253.
Found 9-bit adder for signal <n0644> created at line 1253.
Found 256x9-bit Read Only RAM for signal <_n1016>
Summary:
inferred 1 RAM(s).
inferred 3 Adder/Subtractor(s).
inferred 7 D-type flip-flop(s).
inferred 29 Multiplexer(s).
Unit <vdp18_ctrl> synthesized.
Synthesizing Unit <vdp18_cpuio>.
Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_cpuio.vhd".
Found 1-bit register for signal <int_n_q>.
Found 8-bit register for signal <buffer_q>.
Found 8-bit register for signal <tmp_q>.
Found 8-bit register for signal <ctrl_reg_q<7>>.
Found 8-bit register for signal <ctrl_reg_q<6>>.
Found 8-bit register for signal <ctrl_reg_q<5>>.
Found 8-bit register for signal <ctrl_reg_q<4>>.
Found 8-bit register for signal <ctrl_reg_q<3>>.
Found 8-bit register for signal <ctrl_reg_q<2>>.
Found 8-bit register for signal <ctrl_reg_q<1>>.
Found 8-bit register for signal <ctrl_reg_q<0>>.
Found 14-bit register for signal <addr_q>.
Found 4-bit register for signal <palette_idx_o>.
Found 4-bit register for signal <palette_idx_s>.
Found 4-bit register for signal <state_q>.
Found 5-bit register for signal <sprite_5th_num_q>.
Found 2-bit register for signal <cnt_v>.
Found 1-bit register for signal <rdvram_sched_q>.
Found 1-bit register for signal <rdvram_q>.
Found 1-bit register for signal <wrvram_sched_q>.
Found 1-bit register for signal <wrvram_q>.
Found 1-bit register for signal <wrpal_byte2_s>.
Found 1-bit register for signal <seq.write_pal_v>.
Found 1-bit register for signal <status_reg_s<2>>.
Found 1-bit register for signal <status_reg_s<1>>.
Found 1-bit register for signal <ntsc_pal_s>.
Found 1-bit register for signal <wait_o>.
Found 1-bit register for signal <incr_palidx_s>.
Found 16-bit register for signal <palette_val_s>.
Found 1-bit register for signal <reg_if.incr_palidx_v>.
Found finite state machine <FSM_0> for signal <state_q>.
-----------------------------------------------------------------------
| States | 10 |
| Transitions | 42 |
| Inputs | 7 |
| Outputs | 10 |
| Clock | clock_i (rising_edge) |
| Reset | reset_i (positive) |
| Reset type | asynchronous |
| Reset State | st_idle |
| Power Up State | st_idle |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 14-bit adder for signal <addr_q[0]_GND_49_o_add_3_OUT> created at line 1241.
Found 4-bit adder for signal <palette_idx_s[0]_GND_49_o_add_60_OUT> created at line 1241.
Found 2-bit subtractor for signal <GND_49_o_GND_49_o_sub_159_OUT<1:0>> created at line 654.
Found 8x2-bit Read Only RAM for signal <opmode_o>
Found 3-bit 4-to-1 multiplexer for signal <access_ctrl.transfer_mode_v> created at line 402.
WARNING:Xst:737 - Found 1-bit latch for signal <wait_s>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Summary:
inferred 1 RAM(s).
inferred 3 Adder/Subtractor(s).
inferred 138 D-type flip-flop(s).
inferred 1 Latch(s).
inferred 29 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <vdp18_cpuio> synthesized.
Synthesizing Unit <vdp18_addr_mux>.
Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_addr_mux.vhd".
WARNING:Xst:647 - Input <num_line_i<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <num_line_i<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 14-bit 3-to-1 multiplexer for signal <opmode_i[1]_GND_52_o_wide_mux_2_OUT> created at line 117.
Found 14-bit 13-to-1 multiplexer for signal <vram_a_o> created at line 105.
Summary:
inferred 17 Multiplexer(s).
Unit <vdp18_addr_mux> synthesized.
Synthesizing Unit <vdp18_pattern>.
Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_pattern.vhd".
WARNING:Xst:647 - Input <num_line_i<1:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 8-bit register for signal <pat_name_q>.
Found 8-bit register for signal <pat_tmp_q>.
Found 8-bit register for signal <pat_shift_q>.
Found 8-bit register for signal <pat_col_q>.
Found 10-bit register for signal <pat_cnt_q>.
Found 10-bit adder for signal <pat_cnt_q[0]_GND_53_o_add_0_OUT> created at line 1241.
Found 10-bit subtractor for signal <GND_53_o_GND_53_o_sub_16_OUT<9:0>> created at line 1308.
Found 10-bit subtractor for signal <GND_53_o_GND_53_o_sub_19_OUT<9:0>> created at line 1308.
Summary:
inferred 3 Adder/Subtractor(s).
inferred 42 D-type flip-flop(s).
inferred 19 Multiplexer(s).
Unit <vdp18_pattern> synthesized.
Synthesizing Unit <vdp18_sprite>.
Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_sprite.vhd".
Found 5-bit register for signal <sprite_numbers_q<1>>.
Found 5-bit register for signal <sprite_numbers_q<2>>.
Found 5-bit register for signal <sprite_numbers_q<3>>.
Found 5-bit register for signal <sprite_num_q>.
Found 5-bit register for signal <sprite_numbers_q<0>>.
Found 3-bit register for signal <sprite_idx_q>.
Found 4-bit register for signal <sprite_line_q>.
Found 4-bit register for signal <sprite_cols_q<0>>.
Found 4-bit register for signal <sprite_cols_q<1>>.
Found 4-bit register for signal <sprite_cols_q<2>>.
Found 4-bit register for signal <sprite_cols_q<3>>.
Found 4-bit register for signal <sprite_ec_q>.
Found 4-bit register for signal <sprite_xtog_q>.
Found 8-bit register for signal <sprite_name_q>.
Found 8-bit register for signal <sprite_xpos_q<0>>.
Found 8-bit register for signal <sprite_xpos_q<1>>.
Found 8-bit register for signal <sprite_xpos_q<2>>.
Found 8-bit register for signal <sprite_xpos_q<3>>.
Found 16-bit register for signal <sprite_pats_q<0>>.
Found 16-bit register for signal <sprite_pats_q<1>>.
Found 16-bit register for signal <sprite_pats_q<2>>.
Found 16-bit register for signal <sprite_pats_q<3>>.
Found 10-bit subtractor for signal <n0526> created at line 304.
Found 3-bit adder for signal <sprite_idx_q[0]_GND_54_o_add_0_OUT> created at line 1241.
Found 5-bit adder for signal <sprite_num_q[0]_GND_54_o_add_59_OUT> created at line 1241.
Found 3-bit adder for signal <GND_54_o_GND_54_o_add_203_OUT> created at line 1241.
Found 3-bit adder for signal <GND_54_o_GND_54_o_add_207_OUT> created at line 1241.
Found 3-bit adder for signal <GND_54_o_GND_54_o_add_211_OUT> created at line 1241.
Found 3-bit subtractor for signal <GND_54_o_GND_54_o_sub_2_OUT<2:0>> created at line 1308.
Found 8-bit subtractor for signal <GND_54_o_GND_54_o_sub_8_OUT<7:0>> created at line 1308.
Found 8-bit subtractor for signal <GND_54_o_GND_54_o_sub_13_OUT<7:0>> created at line 1308.
Found 8-bit subtractor for signal <GND_54_o_GND_54_o_sub_18_OUT<7:0>> created at line 1308.
Found 8-bit subtractor for signal <GND_54_o_GND_54_o_sub_23_OUT<7:0>> created at line 1308.
Found 5-bit 4-to-1 multiplexer for signal <sprite_idx_q[1]_sprite_numbers_q[3][0]_wide_mux_216_OUT> created at line 437.
Found 3-bit comparator greater for signal <GND_54_o_sprite_idx_q[0]_LessThan_4_o> created at line 151
Found 3-bit comparator greater for signal <sprite_idx_q[0]_PWR_37_o_LessThan_61_o> created at line 217
Found 9-bit comparator greater for signal <PWR_37_o_vram_d_i[0]_LessThan_181_o> created at line 299
Found 9-bit comparator lessequal for signal <n0307> created at line 311
Found 9-bit comparator greater for signal <GND_54_o_num_line_i[0]_LessThan_184_o> created at line 314
Found 9-bit comparator greater for signal <GND_54_o_num_line_i[0]_LessThan_185_o> created at line 319
Found 3-bit comparator greater for signal <spr_coll_o> created at line 426
Summary:
inferred 11 Adder/Subtractor(s).
inferred 160 D-type flip-flop(s).
inferred 7 Comparator(s).
inferred 148 Multiplexer(s).
Unit <vdp18_sprite> synthesized.
Synthesizing Unit <vdp18_col_mux>.
Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_col_mux.vhd".
Summary:
inferred 7 Multiplexer(s).
Unit <vdp18_col_mux> synthesized.
Synthesizing Unit <vdp18_palette>.
Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_palette.vhd".
Found 16-bit register for signal <ram_q<14>>.
Found 16-bit register for signal <ram_q<13>>.
Found 16-bit register for signal <ram_q<12>>.
Found 16-bit register for signal <ram_q<11>>.
Found 16-bit register for signal <ram_q<10>>.
Found 16-bit register for signal <ram_q<9>>.
Found 16-bit register for signal <ram_q<8>>.
Found 16-bit register for signal <ram_q<7>>.
Found 16-bit register for signal <ram_q<6>>.
Found 16-bit register for signal <ram_q<5>>.
Found 16-bit register for signal <ram_q<4>>.
Found 16-bit register for signal <ram_q<3>>.
Found 16-bit register for signal <ram_q<2>>.
Found 16-bit register for signal <ram_q<1>>.
Found 16-bit register for signal <ram_q<0>>.
Found 16-bit register for signal <ram_q<15>>.
Found 4-bit register for signal <read_addr_q>.
INFO:Xst:3019 - HDL ADVISOR - 256 flip-flops were inferred for signal <ram_q>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
Found 16-bit 16-to-1 multiplexer for signal <data_o> created at line 102.
Summary:
inferred 260 D-type flip-flop(s).
inferred 1 Multiplexer(s).
Unit <vdp18_palette> synthesized.
Synthesizing Unit <dblscan>.
Related source file is "D:\msx1fpga-master\src\video\dblscan.vhd".
INFO:Xst:3210 - "D:\msx1fpga-master\src\video\dblscan.vhd" line 103: Output port <data_a_o> of the instance <u_ram_a> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "D:\msx1fpga-master\src\video\dblscan.vhd" line 119: Output port <data_a_o> of the instance <u_ram_b> is unconnected or connected to loadless signal.
Found 1-bit register for signal <vsync_n_t1_s>.
Found 1-bit register for signal <ibank_s>.
Found 9-bit register for signal <hpos_s>.
Found 9-bit register for signal <hpos_o_s>.
Found 1-bit register for signal <oddline_s>.
Found 1-bit register for signal <obank_s>.
Found 3-bit register for signal <vs_cnt_s>.
Found 1-bit register for signal <ohs_s>.
Found 1-bit register for signal <ohs_t1_s>.
Found 1-bit register for signal <ovs_s>.
Found 1-bit register for signal <ovs_t1_s>.
Found 1-bit register for signal <hsync_n_o>.
Found 1-bit register for signal <hblank_o>.
Found 4-bit register for signal <col_o>.
Found 1-bit register for signal <vsync_n_o>.
Found 1-bit register for signal <hsync_n_t1_s>.
Found 9-bit adder for signal <hpos_s[8]_GND_58_o_add_0_OUT> created at line 159.
Found 9-bit adder for signal <hpos_o_s[8]_GND_58_o_add_5_OUT> created at line 176.
Found 3-bit adder for signal <vs_cnt_s[2]_GND_58_o_add_7_OUT> created at line 186.
Found 9-bit comparator lessequal for signal <hpos_o_s[8]_GND_58_o_LessThan_16_o> created at line 207
Found 9-bit comparator greater for signal <hpos_o_s[8]_GND_58_o_LessThan_17_o> created at line 212
Found 9-bit comparator greater for signal <PWR_42_o_hpos_o_s[8]_LessThan_18_o> created at line 212
Summary:
inferred 3 Adder/Subtractor(s).
inferred 37 D-type flip-flop(s).
inferred 3 Comparator(s).
inferred 1 Multiplexer(s).
Unit <dblscan> synthesized.
Synthesizing Unit <dpram_1>.
Related source file is "D:\msx1fpga-master\src\ram\dpram.vhd".
addr_width_g = 9
data_width_g = 4
Found 9-bit register for signal <read_addr_b_q>.
Found 9-bit register for signal <read_addr_a_q>.
Found 512x4-bit dual-port RAM <Mram_ram_q> for signal <ram_q>.
Summary:
inferred 2 RAM(s).
inferred 18 D-type flip-flop(s).
Unit <dpram_1> synthesized.
Synthesizing Unit <YM2149>.
Related source file is "D:\msx1fpga-master\src\audio\YM2149.vhd".
Found 8-bit register for signal <regs_q<0>>.
Found 8-bit register for signal <regs_q<1>>.
Found 8-bit register for signal <regs_q<2>>.
Found 8-bit register for signal <regs_q<3>>.
Found 8-bit register for signal <regs_q<4>>.
Found 8-bit register for signal <regs_q<5>>.
Found 8-bit register for signal <regs_q<6>>.
Found 8-bit register for signal <regs_q<8>>.
Found 8-bit register for signal <regs_q<9>>.
Found 8-bit register for signal <regs_q<10>>.
Found 8-bit register for signal <regs_q<11>>.
Found 8-bit register for signal <regs_q<12>>.
Found 8-bit register for signal <regs_q<13>>.
Found 8-bit register for signal <regs_q<14>>.
Found 8-bit register for signal <regs_q<15>>.
Found 8-bit register for signal <reg_addr_q>.
Found 8-bit register for signal <regs_q<7>>.
Found 1-bit register for signal <ena_div>.
Found 1-bit register for signal <ena_div_noise>.
Found 4-bit register for signal <cnt_div>.
Found 1-bit register for signal <noise_div>.
Found 5-bit register for signal <noise_gen_cnt>.
Found 17-bit register for signal <poly17>.
Found 12-bit register for signal <tone_gen_cnt<1>>.
Found 12-bit register for signal <tone_gen_cnt<2>>.
Found 12-bit register for signal <tone_gen_cnt<3>>.
Found 3-bit register for signal <tone_gen_op>.
Found 1-bit register for signal <env_ena>.
Found 16-bit register for signal <env_gen_cnt>.
Found 5-bit register for signal <env_vol>.
Found 1-bit register for signal <env_inc>.
Found 1-bit register for signal <env_hold>.
Found 5-bit register for signal <A>.
Found 5-bit register for signal <B>.
Found 5-bit register for signal <C>.
Found 8-bit register for signal <audio_ch_mix_o>.
Found 8-bit register for signal <audio_ch_a_o>.
Found 8-bit register for signal <audio_ch_b_o>.
Found 8-bit register for signal <audio_ch_c_o>.
Found 5-bit adder for signal <noise_gen_cnt[4]_GND_60_o_add_55_OUT> created at line 1241.
Found 12-bit adder for signal <tone_gen_cnt[1][11]_GND_60_o_add_74_OUT> created at line 1241.
Found 12-bit adder for signal <tone_gen_cnt[2][11]_GND_60_o_add_78_OUT> created at line 1241.
Found 12-bit adder for signal <tone_gen_cnt[3][11]_GND_60_o_add_82_OUT> created at line 1241.
Found 16-bit adder for signal <env_gen_cnt[15]_GND_60_o_add_103_OUT> created at line 1241.
Found 5-bit adder for signal <env_vol[4]_GND_60_o_add_113_OUT> created at line 428.
Found 5-bit adder for signal <env_vol[4]_PWR_44_o_add_114_OUT> created at line 430.
Found 10-bit adder for signal <n0425> created at line 547.
Found 10-bit adder for signal <n0344> created at line 547.
Found 4-bit subtractor for signal <GND_60_o_GND_60_o_sub_47_OUT<3:0>> created at line 277.
Found 5-bit subtractor for signal <GND_60_o_GND_60_o_sub_52_OUT<4:0>> created at line 1308.
Found 12-bit subtractor for signal <GND_60_o_GND_60_o_sub_66_OUT<11:0>> created at line 1308.
Found 12-bit subtractor for signal <GND_60_o_GND_60_o_sub_69_OUT<11:0>> created at line 1308.
Found 12-bit subtractor for signal <GND_60_o_GND_60_o_sub_72_OUT<11:0>> created at line 1308.
Found 16-bit subtractor for signal <GND_60_o_GND_60_o_sub_101_OUT<15:0>> created at line 1308.
Found 8x1-bit Read Only RAM for signal <busctrl_addr_s>
Found 32x8-bit Read Only RAM for signal <A[4]_A[4]_mux_153_OUT>
Found 32x8-bit Read Only RAM for signal <B[4]_B[4]_mux_154_OUT>
Found 32x8-bit Read Only RAM for signal <C[4]_C[4]_mux_155_OUT>
Found 8-bit 16-to-1 multiplexer for signal <reg_addr_q[3]_regs_q[15][7]_wide_mux_41_OUT> created at line 229.
Found 5-bit comparator greater for signal <n0070> created at line 302
Found 12-bit comparator lessequal for signal <n0092> created at line 338
Found 12-bit comparator lessequal for signal <n0100> created at line 338
Found 12-bit comparator lessequal for signal <n0108> created at line 338
Found 16-bit comparator lessequal for signal <n0128> created at line 368
Summary:
inferred 4 RAM(s).
inferred 14 Adder/Subtractor(s).
inferred 275 D-type flip-flop(s).
inferred 5 Comparator(s).
inferred 25 Multiplexer(s).
Unit <YM2149> synthesized.
Synthesizing Unit <PIO>.
Related source file is "D:\msx1fpga-master\src\peripheral\pio.vhd".
Found 8-bit register for signal <portc_r>.
Found 1-bit register for signal <porta_r<7>>.
Found 1-bit register for signal <porta_r<6>>.
Found 1-bit register for signal <porta_r<5>>.
Found 1-bit register for signal <porta_r<4>>.
Found 1-bit register for signal <porta_r<3>>.
Found 1-bit register for signal <porta_r<2>>.
Found 1-bit register for signal <porta_r<1>>.
Found 1-bit register for signal <porta_r<0>>.
Summary:
inferred 16 D-type flip-flop(s).
inferred 14 Multiplexer(s).
Unit <PIO> synthesized.
Synthesizing Unit <exp_slot>.
Related source file is "D:\msx1fpga-master\src\peripheral\exp_slot.vhd".
Found 1-bit register for signal <exp_reg_s<7>>.
Found 1-bit register for signal <exp_reg_s<6>>.
Found 1-bit register for signal <exp_reg_s<5>>.
Found 1-bit register for signal <exp_reg_s<4>>.
Found 1-bit register for signal <exp_reg_s<3>>.
Found 1-bit register for signal <exp_reg_s<2>>.
Found 1-bit register for signal <exp_reg_s<1>>.
Found 1-bit register for signal <exp_reg_s<0>>.
Found 2-bit 4-to-1 multiplexer for signal <exp_sel_s> created at line 95.
Summary:
inferred 8 D-type flip-flop(s).
inferred 5 Multiplexer(s).
Unit <exp_slot> synthesized.
Synthesizing Unit <swioports>.
Related source file is "D:\msx1fpga-master\src\peripheral\swioports.vhd".
Found 8-bit register for signal <reg_addr_q>.
Found 8-bit register for signal <maker_id_s>.
Found 5-bit register for signal <index_v>.
Found 2-bit register for signal <mapper_q>.
Found 1-bit register for signal <turbo_on_q>.
Found 1-bit register for signal <vga_en_q>.
Found 1-bit register for signal <reading_v>.
Found 1-bit register for signal <nextor_en_q>.
Found 1-bit register for signal <softreset_q>.
Found 1-bit register for signal <keymap_we_s>.
Found 2-bit register for signal <turbo_on_de_v>.
Found 2-bit register for signal <vga_on_de_v>.
Found 10-bit register for signal <keymap_addr_q>.
Found 8-bit register for signal <keymap_data_q>.
Found 1-bit register for signal <keymap_we_a_v>.
Found 1-bit register for signal <has_data_regv_s>.
Found 8-bit register for signal <reg_data_s>.
Found 10-bit adder for signal <keymap_addr_q[9]_GND_77_o_add_64_OUT> created at line 1241.
Found 5-bit adder for signal <index_v[4]_GND_77_o_add_110_OUT> created at line 287.
Found 8-bit 7-to-1 multiplexer for signal <_n0343> created at line 241.
Found 5-bit comparator lessequal for signal <index_v[4]_GND_77_o_LessThan_110_o> created at line 286
Summary:
inferred 2 Adder/Subtractor(s).
inferred 61 D-type flip-flop(s).
inferred 1 Comparator(s).
inferred 36 Multiplexer(s).
Unit <swioports> synthesized.
Synthesizing Unit <spi>.
Related source file is "D:\msx1fpga-master\src\peripheral\spi.vhd".
Found 1-bit register for signal <spi_cs_n_o>.
Found 4-bit register for signal <counter_s>.
Found 8-bit register for signal <port1_r>.
Found 9-bit register for signal <shift_r>.
Found 1-bit register for signal <sck_delayed_s>.
Found 4-bit adder for signal <counter_s[3]_GND_142_o_add_7_OUT> created at line 1241.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 23 D-type flip-flop(s).
inferred 7 Multiplexer(s).
Unit <spi> synthesized.
Synthesizing Unit <romnextor>.
Related source file is "D:\msx1fpga-master\src\peripheral\romnextor.vhd".
WARNING:Xst:647 - Input <data_i<7:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 3-bit register for signal <rom_page_s>.
Summary:
inferred 3 D-type flip-flop(s).
inferred 2 Multiplexer(s).
Unit <romnextor> synthesized.
Synthesizing Unit <escci>.
Related source file is "D:\msx1fpga-master\src\peripheral\escci\escci.vhd".
Found 8-bit register for signal <SccBank0>.
Found 8-bit register for signal <SccModeA>.
Found 8-bit register for signal <SccModeB>.
Found 8-bit register for signal <SccBank2>.
Found 8-bit register for signal <SccBank3>.
Found 8-bit register for signal <SccBank1>.
Found 1-bit register for signal <wav_copy_s>.
Found 1-bit register for signal <flag_v>.
Found 1-bit register for signal <cs_dly_s>.
Found 1-bit 4-to-1 multiplexer for signal <ram_addr_o<18>> created at line 56.
Found 1-bit 4-to-1 multiplexer for signal <ram_addr_o<17>> created at line 56.
Found 1-bit 4-to-1 multiplexer for signal <ram_addr_o<16>> created at line 56.
Found 1-bit 4-to-1 multiplexer for signal <ram_addr_o<15>> created at line 56.
Found 1-bit 4-to-1 multiplexer for signal <ram_addr_o<14>> created at line 56.
Found 1-bit 4-to-1 multiplexer for signal <ram_addr_o<13>> created at line 56.
Found 8-bit 4-to-1 multiplexer for signal <data_o> created at line 51.
Summary:
inferred 51 D-type flip-flop(s).
inferred 22 Multiplexer(s).
Unit <escci> synthesized.
Synthesizing Unit <scc_wave>.
Related source file is "D:\msx1fpga-master\src\peripheral\escci\scc_wave.vhd".
Found 12-bit register for signal <reg_freq_ch_a>.
Found 12-bit register for signal <reg_freq_ch_b>.
Found 12-bit register for signal <reg_freq_ch_c>.
Found 12-bit register for signal <reg_freq_ch_d>.
Found 12-bit register for signal <reg_freq_ch_e>.
Found 12-bit register for signal <ff_cnt_ch_a>.
Found 12-bit register for signal <ff_cnt_ch_b>.
Found 12-bit register for signal <ff_cnt_ch_c>.
Found 12-bit register for signal <ff_cnt_ch_d>.
Found 12-bit register for signal <ff_cnt_ch_e>.
Found 4-bit register for signal <reg_vol_ch_a>.
Found 4-bit register for signal <reg_vol_ch_b>.
Found 4-bit register for signal <reg_vol_ch_c>.
Found 4-bit register for signal <reg_vol_ch_d>.
Found 4-bit register for signal <reg_vol_ch_e>.
Found 5-bit register for signal <reg_ch_sel>.
Found 5-bit register for signal <ff_ptr_ch_a>.
Found 5-bit register for signal <ff_ptr_ch_b>.
Found 5-bit register for signal <ff_ptr_ch_c>.
Found 5-bit register for signal <ff_ptr_ch_d>.
Found 5-bit register for signal <ff_ptr_ch_e>.
Found 8-bit register for signal <reg_mode_sel>.
Found 8-bit register for signal <ff_wave_dat>.
Found 3-bit register for signal <ff_ch_num_dl>.
Found 3-bit register for signal <ff_ch_num>.
Found 15-bit register for signal <ff_mix>.
Found 15-bit register for signal <ff_wave>.
Found 1-bit register for signal <ff_rst_ch_a>.
Found 1-bit register for signal <ff_rst_ch_b>.
Found 1-bit register for signal <ff_rst_ch_c>.
Found 1-bit register for signal <ff_rst_ch_d>.
Found 1-bit register for signal <ff_rst_ch_e>.
Found 1-bit register for signal <ff_req_dl>.
Found 5-bit adder for signal <ff_ptr_ch_a[4]_GND_146_o_add_47_OUT> created at line 244.
Found 5-bit adder for signal <ff_ptr_ch_b[4]_GND_146_o_add_55_OUT> created at line 254.
Found 5-bit adder for signal <ff_ptr_ch_c[4]_GND_146_o_add_63_OUT> created at line 264.
Found 5-bit adder for signal <ff_ptr_ch_d[4]_GND_146_o_add_71_OUT> created at line 274.
Found 5-bit adder for signal <ff_ptr_ch_e[4]_GND_146_o_add_79_OUT> created at line 284.
Found 3-bit adder for signal <ff_ch_num[2]_GND_146_o_add_120_OUT> created at line 379.
Found 15-bit adder for signal <w_mul[11]_ff_mix[14]_add_124_OUT> created at line 393.
Found 12-bit subtractor for signal <GND_146_o_GND_146_o_sub_49_OUT<11:0>> created at line 247.
Found 12-bit subtractor for signal <GND_146_o_GND_146_o_sub_57_OUT<11:0>> created at line 257.
Found 12-bit subtractor for signal <GND_146_o_GND_146_o_sub_65_OUT<11:0>> created at line 267.
Found 12-bit subtractor for signal <GND_146_o_GND_146_o_sub_73_OUT<11:0>> created at line 277.
Found 12-bit subtractor for signal <GND_146_o_GND_146_o_sub_81_OUT<11:0>> created at line 287.
Found 8x5-bit Read Only RAM for signal <w_ch_dec>
Found 4-bit 7-to-1 multiplexer for signal <w_ch_vol> created at line 337.
Found 8-bit 4-to-1 multiplexer for signal <_n0386> created at line 82.
Found 8-bit comparator greater for signal <addr_i[7]_PWR_105_o_LessThan_1_o> created at line 143
Summary:
inferred 1 RAM(s).
inferred 12 Adder/Subtractor(s).
inferred 228 D-type flip-flop(s).
inferred 1 Comparator(s).
inferred 31 Multiplexer(s).
Unit <scc_wave> synthesized.
Synthesizing Unit <dpram_2>.
Related source file is "D:\msx1fpga-master\src\ram\dpram.vhd".
addr_width_g = 8
data_width_g = 8
Found 8-bit register for signal <read_addr_b_q>.
Found 8-bit register for signal <read_addr_a_q>.
Found 256x8-bit dual-port RAM <Mram_ram_q> for signal <ram_q>.
Summary:
inferred 2 RAM(s).
inferred 16 D-type flip-flop(s).
Unit <dpram_2> synthesized.
Synthesizing Unit <scc_wave_mul>.
Related source file is "D:\msx1fpga-master\src\peripheral\escci\scc_wave.vhd".
Found 8x5-bit multiplier for signal <w_mul> created at line 52.
Summary:
inferred 1 Multiplier(s).
Unit <scc_wave_mul> synthesized.
Synthesizing Unit <mainrom>.
Related source file is "D:\msx1fpga-master\src\rom\mainrom.vhd".
Found 8-bit register for signal <data>.
Found 32768x8-bit Read Only RAM for signal <addr[14]_GND_160_o_wide_mux_0_OUT>
Summary:
inferred 1 RAM(s).
inferred 8 D-type flip-flop(s).
Unit <mainrom> synthesized.
Synthesizing Unit <keyboard>.
Related source file is "D:\msx1fpga-master\src\peripheral\keyboard.vhd".
Found 8-bit register for signal <cols_o>.
Found 4-bit register for signal <extra_keys_s>.
Found 3-bit register for signal <skip_count_v>.
Found 3-bit register for signal <keymap_seq_s>.
Found 2-bit register for signal <extended_v>.
Found 2-bit register for signal <extended_s>.
Found 8-bit register for signal <matrix_s<15>>.
Found 8-bit register for signal <matrix_s<14>>.
Found 8-bit register for signal <matrix_s<13>>.
Found 8-bit register for signal <matrix_s<12>>.
Found 8-bit register for signal <matrix_s<11>>.
Found 8-bit register for signal <matrix_s<10>>.
Found 8-bit register for signal <matrix_s<9>>.
Found 8-bit register for signal <matrix_s<8>>.
Found 8-bit register for signal <matrix_s<7>>.
Found 8-bit register for signal <matrix_s<6>>.
Found 8-bit register for signal <matrix_s<5>>.
Found 8-bit register for signal <matrix_s<4>>.
Found 8-bit register for signal <matrix_s<3>>.
Found 8-bit register for signal <matrix_s<2>>.
Found 8-bit register for signal <matrix_s<1>>.
Found 8-bit register for signal <matrix_s<0>>.
Found 10-bit register for signal <keymap_addr_s>.
Found 1-bit register for signal <reset_o>.
Found 1-bit register for signal <por_o>.
Found 1-bit register for signal <ed_resp_v>.
Found 1-bit register for signal <break_v>.
Found 1-bit register for signal <shift_v>.
Found 1-bit register for signal <ctrl_v>.
Found 1-bit register for signal <alt_v>.
Found 1-bit register for signal <has_keycode_s>.
Found 1-bit register for signal <break_s>.
Found 1-bit register for signal <shift_s>.
Found 1-bit register for signal <reload_core_o>.
Found 1-bit register for signal <data_load_s>.
Found 1-bit register for signal <batcode_v>.
Found 8-bit register for signal <d_to_send_s>.
Found 1-bit register for signal <led_caps_v>.
Found 4-bit register for signal <row_v>.
Found 3-bit register for signal <col_v>.
Found 1-bit register for signal <mod_shift_v>.
Found finite state machine <FSM_1> for signal <keymap_seq_s>.
-----------------------------------------------------------------------
| States | 5 |
| Transitions | 6 |
| Inputs | 1 |
| Outputs | 3 |
| Clock | clock_i (rising_edge) |
| Reset | reset_i (positive) |
| Reset type | asynchronous |
| Reset State | km_idle |
| Power Up State | km_idle |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found finite state machine <FSM_2> for signal <extended_v>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 35 |
| Inputs | 10 |
| Outputs | 5 |
| Clock | clock_i (rising_edge) |
| Reset | reset_i (positive) |
| Reset type | asynchronous |
| Reset State | 00 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 3-bit subtractor for signal <GND_161_o_GND_161_o_sub_4_OUT<2:0>> created at line 161.
Found 8-bit 16-to-1 multiplexer for signal <rows_coded_i[3]_matrix_s[15][7]_wide_mux_71_OUT> created at line 255.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 185 D-type flip-flop(s).
inferred 162 Multiplexer(s).
inferred 2 Finite State Machine(s).
Unit <keyboard> synthesized.
Synthesizing Unit <ps2_iobase>.
Related source file is "D:\msx1fpga-master\src\peripheral\ps2_iobase.vhd".
Found 2-bit register for signal <dat_sync_v>.
Found 2-bit register for signal <clk_sync_v>.
Found 16-bit register for signal <edge_detect_v>.
Found 8-bit register for signal <sdata_s>.
Found 1-bit register for signal <data_rdy_o>.
Found 4-bit register for signal <_v4>.
Found 16-bit register for signal <timeout_q>.
Found 1-bit register for signal <sigsending_s>.
Found 8-bit register for signal <hdata_s>.
Found 1-bit register for signal <sigclkreleased>.
Found 1-bit register for signal <sigclkheld>.
Found 9-bit register for signal <count_v>.
Found 1-bit register for signal <count_v[8]_clock_i_DFF_220>.
Found 1-bit register for signal <ps2_data_io_clock_i_DFF_221_q>.
Found 1-bit register for signal <sigsendend_s>.
Found 4-bit register for signal <TOPS2.count_v>.
Found 1-bit register for signal <ps2_clk_io_clock_i_DFF_217_q>.
Found 1-bit register for signal <PWR_128_o_clock_i_DFF_223>.
Found 4-bit adder for signal <count_v[3]_GND_162_o_add_12_OUT> created at line 117.
Found 16-bit adder for signal <timeout_q[15]_GND_162_o_add_18_OUT> created at line 1241.
Found 9-bit adder for signal <count_v[8]_GND_162_o_add_36_OUT> created at line 169.
Found 4-bit adder for signal <TOPS2.count_v[3]_GND_162_o_add_48_OUT> created at line 216.
Found 3-bit subtractor for signal <GND_162_o_GND_162_o_sub_9_OUT<2:0>> created at line 110.
Found 1-bit 8-to-1 multiplexer for signal <TOPS2.count_v[2]_hdata_s[7]_Mux_43_o> created at line 200.
Found 1-bit tristate buffer for signal <ps2_clk_io> created at line 152
Found 1-bit tristate buffer for signal <ps2_data_io> created at line 184
Found 4-bit comparator lessequal for signal <count_v[3]_PWR_128_o_LessThan_8_o> created at line 109
Found 9-bit comparator greater for signal <count_v[8]_PWR_128_o_LessThan_34_o> created at line 163
Found 9-bit comparator greater for signal <count_v[8]_PWR_128_o_LessThan_36_o> created at line 168
Found 4-bit comparator greater for signal <TOPS2.count_v[3]_PWR_128_o_LessThan_43_o> created at line 199
Summary:
inferred 5 Adder/Subtractor(s).
inferred 78 D-type flip-flop(s).
inferred 4 Comparator(s).
inferred 21 Multiplexer(s).
inferred 2 Tristate(s).
Unit <ps2_iobase> synthesized.
Synthesizing Unit <keymap>.
Related source file is "D:\msx1fpga-master\src\peripheral\keymap.vhd".
Found 1024x8-bit dual-port RAM <Mram_ram_q> for signal <ram_q>.
Found 10-bit register for signal <read_addr_q>.
Summary:
inferred 1 RAM(s).
inferred 10 D-type flip-flop(s).
Unit <keymap> synthesized.
.
.
.
.
.
.
.
.
.
All constraints were met.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 3 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 54 secs
Total CPU time to PAR completion (all processors): 1 mins 2 secs
Peak Memory Usage: 420 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 5
Number of info messages: 0
Writing design to file zxuno_top.ncd
PAR done!
D:\msx1fpga-master\synth\zxuno>call C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\trce -intstyle ise -v 3 -s -n 3 -fastpaths -xml zxuno_top.twx zxuno_top.ncd -o zxuno_top.twr zxuno_top.pcf
ERROR:Portability:90 - Command line error: Argument <speed> must be specified
for the switch "-s".
Usage: trce.exe [-e|-v [<limit:0,2000000000>]] [-l <limit:0,2000000000>] [-n
[<limit:0,2000000000>]] [-u [<limit:0,2000000000>]] [-a] [-s <speed>] [-o
<report[.twr]>] [-stamp <stampfile>] [-tsi <tsifile[.tsi]>] [-xml
<report[.twx]>] [-nodatasheet] [-timegroups] [-fastpaths] [-noflight] [-intstyle
ise|xflow|silent] [-ise <projectfile>] [-filter <filter_file[.filter]>]
<design[.ncd]> [<constraint[.pcf]>]
<design[.ncd]> ... Xilinx physical design file (no default)
<constraint[.pcf]> ... optional physical constraint file (default design.pcf)
-o <report[.twr]> ... report output file (default design.twr)
-xml <report[.twx]> ... XML report output file (default design.twx)
-e [<limit>] ... produce detailed error report for timing constraints
optionally limited to the number of items specified by
<limit>
-v [<limit>] ... produce verbose timing report for timing constraints
optionally limited to the number of items specified by
<limit>
-l [<limit>] ... produce timing report for timing constraints
optionally limited to the number of items specified by
<limit>
-n [<limit>] ... report paths per endpoint (default is per constraint).
Limited to the number of endpoints specified by <limit>.
Worst value between setup and hold is used to identify
endpoint to report, using that endpoint for both setup
and hold details. Use -fastpaths, to report unique
endpoints for worst setup and worst hold. The -v <limit>
value, dictates the number of reported paths per
endpoint. This switch requries -v or -e
-s <speed> ... run analysis with the speed grade specified by <speed>.
This switch requries -v or -e
-a ... perform advanced design analysis in the absence
of a physical constraint file. This switch requires
-v or -e
-u [<limit>] ... report unconstrained paths optionally limited to the
number of items specified by <limit>. This switch
requries -v or -e
-f <filename> ... use the file specified by <filename> as command input
-stamp <stampfile> ... optionally generate STAMP model and data files. This
switch requires -v or -e
-tsi <tsifile[.tsi]> ... produce timing specification interaction report. This
switch requries -v or -e
-nodatasheet ... do not create the datasheet section of the report. This
switch requires -v or -e
-timegroups ... create the table of timegroups section of the report
This switch requires -v or -e
-fastpaths ... report fastest paths/verbose hold paths. This switch
requires -v or -e
-filter <filter_file[.filter] ... Message Filter file name (for example
"filter.filter"). If specified, the contents of this
file will be used to filter messages from this
application. The filter file can be created using
Xreport. This switch requires -v or -e
-noflight ... turn off the package flight delay
-intstyle <style> ... use the specified style: ise, xflow, or silent
-ise <projectfile> ... use the ISE project file specified by <projectfile>
TRCE: Creates a Timing Report file (TWR) derived from static timing
analysis of the Physical Design file (NCD). The analysis is typically
based on constraints included in the optional Physical Constraints
file (PCF).
D:\msx1fpga-master\synth\zxuno>call C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\bitgen -intstyle ise -f zxuno_top.ut zxuno_top.ncd
WARNING:Bitgen:300 - The ConfigRate:2 setting will be ignored because the
ExtMasterCclk_en option has been set to Yes.
INFO:Bitgen:341 - This design is using one or more 9K Block RAMs (RAMB8BWER).
9K Block RAM initialization data, both user defined and default, requires a
special bit stream format. For more information, please reference Xilinx
Answer Record 39999.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
the_msx/pio/reset_i_GND_73_o_AND_297_o is sourced by a combinatorial pin.
This is not good design practice. Use the CE pin to control the loading of
data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
the_msx/vdp/hor_vert_b/reset_i_first_line_s[2]_AND_118_o is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
the_msx/vdp/hor_vert_b/reset_i_first_line_s[2]_AND_117_o is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net por_clock_s is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net the_msx/swiop/clock_i_inv
is sourced by a combinatorial pin. This is not good design practice. Use the
CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net clks/clock_out1_s is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
keyb/ps2_port/sigclkheld_enable_i_AND_641_o is sourced by a combinatorial
pin. This is not good design practice. Use the CE pin to control the loading
of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
the_msx/psg/Mram_busctrl_addr_s is sourced by a combinatorial pin. This is
not good design practice. Use the CE pin to control the loading of data into
the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
the_msx/exp/sltsl_n_i_ffff_s_OR_233_o is sourced by a combinatorial pin. This
is not good design practice. Use the CE pin to control the loading of data
into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
the_msx/vdp/cpu_io_b/mode_i[0]_wrvram_q_Mux_125_o is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<the_msx/cpu/u0/Regs/Mram_RegsH11_RAMD_D1_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<the_msx/cpu/u0/Regs/Mram_RegsL11_RAMD_D1_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
D:\msx1fpga-master\synth\zxuno>pause
Presione una tecla para continuar . . .
D:\msx1fpga-master\synth\zxuno>
I would love to run your great work on my ZX-ONE V2.
Thank you very much.
© 1982 Sinclair Research Ltd
- antoniovillena
- Mensajes: 2621
- Registrado: 27 Sep 2015, 20:41
Re: New MSX1 core
I think Fabio support both v3 and v4 versions of ZX-Uno. If send him a tested zxuno_pins_v2.ucf he can put in this folder:
https://github.com/fbelavenuto/msx1fpga ... ynth/zxuno
Fabio, browsing into the repository I've found a comment "HDMI works!". I will test in the future with the HDMI-ESP12 addon. If works I'll send you an addon for free. A guy in the forum (yombo) has ordered yesterday a batch with the new version. It will take a month.
https://github.com/fbelavenuto/msx1fpga ... ynth/zxuno
Fabio, browsing into the repository I've found a comment "HDMI works!". I will test in the future with the HDMI-ESP12 addon. If works I'll send you an addon for free. A guy in the forum (yombo) has ordered yesterday a batch with the new version. It will take a month.
Re: New MSX1 core
I've uploaded the kicad project and gerbers to github, in case someone wants to check it out:antoniovillena escribió: Fabio, browsing into the repository I've found a comment "HDMI works!". I will test in the future with the HDMI-ESP12 addon. If works I'll send you an addon for free. A guy in the forum (yombo) has ordered yesterday a batch with the new version. It will take a month.
He subido el proyecto de kicad y los gerbers a github, por si alguien quiere echarle un ojo.
https://github.com/yomboprime/AddonsZXUnoDic2016
Re: New MSX1 core
I have tested it with a zxuno_pins_v2.ucf adapted from the v4 by me and it still fails in the same thing.antoniovillena escribió:I think Fabio support both v3 and v4 versions of ZX-Uno. If send him a tested zxuno_pins_v2.ucf he can put in this folder:
https://github.com/fbelavenuto/msx1fpga ... ynth/zxuno.
If you want, yourselft can try it.
zxuno_pins_v2.ucf
Código: Seleccionar todo
# Clocks
NET "clock_50_i" LOC="P55" | IOSTANDARD = LVCMOS33;
# Video output
NET "vga_r_o<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "vga_r_o<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "vga_r_o<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "vga_g_o<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "vga_g_o<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "vga_g_o<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "vga_b_o<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "vga_b_o<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "vga_b_o<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
NET "vga_csync_n_o" LOC="P87" | IOSTANDARD = LVCMOS33;
NET "vga_vsync_n_o" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "vga_ntsc_o" LOC="P67" | IOSTANDARD = LVCMOS33;
NET "vga_pal_o" LOC="P66" | IOSTANDARD = LVCMOS33;
# Sound input/output
NET "dac_l_o" LOC="P8" | IOSTANDARD = LVCMOS33;
NET "dac_r_o" LOC="P9" | IOSTANDARD = LVCMOS33;
NET "ear_i" LOC="P105" | IOSTANDARD = LVCMOS33;
# SRAM
NET "sram_addr_o<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
NET "sram_addr_o<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
NET "sram_addr_o<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
NET "sram_addr_o<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
NET "sram_addr_o<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
NET "sram_addr_o<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
NET "sram_addr_o<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
NET "sram_addr_o<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
NET "sram_addr_o<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
NET "sram_addr_o<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
NET "sram_addr_o<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
NET "sram_addr_o<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
NET "sram_addr_o<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
NET "sram_addr_o<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
NET "sram_addr_o<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
NET "sram_addr_o<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
NET "sram_addr_o<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
NET "sram_addr_o<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
NET "sram_addr_o<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
#NET "sram_addr_o<19>" LOC="P" | IOSTANDARD = LVCMOS33;
#NET "sram_addr_o<20>" LOC="P" | IOSTANDARD = LVCMOS33;
NET "sram_data_io<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
NET "sram_data_io<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
NET "sram_data_io<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
NET "sram_data_io<3>" LOC="P99" | IOSTANDARD = LVCMOS33;
NET "sram_data_io<4>" LOC="P100" | IOSTANDARD = LVCMOS33;
NET "sram_data_io<5>" LOC="P101" | IOSTANDARD = LVCMOS33;
NET "sram_data_io<6>" LOC="P102" | IOSTANDARD = LVCMOS33;
NET "sram_data_io<7>" LOC="P104" | IOSTANDARD = LVCMOS33;
NET "sram_we_n_o" LOC="P134" | IOSTANDARD = LVCMOS33;
# Keyboard
NET "ps2_clk_io" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "ps2_data_io" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "ps2_mouse_clk_io" LOC="P94" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "ps2_mouse_data_io" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP;
# SD/MMC
NET "sd_cs_n_o" LOC="P59" | IOSTANDARD = LVCMOS33;
NET "sd_sclk_o" LOC="P75" | IOSTANDARD = LVCMOS33;
NET "sd_mosi_o" LOC="P74" | IOSTANDARD = LVCMOS33;
NET "sd_miso_i" LOC="P78" | IOSTANDARD = LVCMOS33;
# SPI Flash
NET "flash_cs_n_o" LOC="P38" | IOSTANDARD = LVCMOS33;
NET "flash_sclk_o" LOC="P70" | IOSTANDARD = LVCMOS33;
NET "flash_mosi_o" LOC="P64" | IOSTANDARD = LVCMOS33;
NET "flash_miso_i" LOC="P65" | IOSTANDARD = LVCMOS33;
#NET "flash_wp_o" LOC="P62" | IOSTANDARD = LVCMOS33;
#NET "flash_hold_o" LOC="P61" | IOSTANDARD = LVCMOS33;
# Joystick
NET "joy_up_i" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "joy_down_i" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "joy_left_i" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "joy_right_i" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "joy_fire1_i" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "joy_fire2_i" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "joy_fire3_o" LOC="P7" | IOSTANDARD = LVCMOS33;
# GPIO
NET "joy2_btn1_io" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP; # GPIO 6
NET "joy2_btn2_io" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP; # GPIO 7
#NET "gpio_io<6>" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<7>" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<8>" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<9>" LOC="P51" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<10>" LOC="P50" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<11>" LOC="P48" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<12>" LOC="P47" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<13>" LOC="P46" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<14>" LOC="P45" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<15>" LOC="P44" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<16>" LOC="P43" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<17>" LOC="P41" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<18>" LOC="P40" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<19>" LOC="P35" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<20>" LOC="P34" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<21>" LOC="P33" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<22>" LOC="P32" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<23>" LOC="P30" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<24>" LOC="P29" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<25>" LOC="P27" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<26>" LOC="P26" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<27>" LOC="P24" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<28>" LOC="P23" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<29>" LOC="P22" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<30>" LOC="P21" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<31>" LOC="P17" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<32>" LOC="P16" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<33>" LOC="P15" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<34>" LOC="P14" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "gpio_io<35>" LOC="P12" | IOSTANDARD = LVCMOS33 | PULLUP;
# DEBUG
NET "led_o" LOC="P10" | IOSTANDARD = LVCMOS33;
# Clock Constraints
NET "clock_50_i" TNM_NET = clock_50_i;
TIMESPEC TS_clock_50_i = PERIOD "clock_50_i" 20 ns HIGH 50%;
NET "clock_master_s" TNM_NET = clock_master_s;
TIMESPEC TS_clock_master_s = PERIOD "clock_master_s" 46.56 ns HIGH 50%;
NET "clks/clock_3m_s" TNM_NET = clks/clock_3m_s;
TIMESPEC TS_clks_clock_3m_s = PERIOD "clks/clock_3m_s" 279.365 ns HIGH 50%;
NET "clks/clock_vdp_s" TNM_NET = clks/clock_vdp_s;
TIMESPEC TS_clks_clock_vdp_s = PERIOD "clks/clock_vdp_s" 93.121 ns HIGH 50%;
Fixed!
Confirmed that it works correctly on my ZX-UNO V2.
Fabio, can you add this file to your repository if you want.
© 1982 Sinclair Research Ltd
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- Mensajes: 100
- Registrado: 08 Sep 2016, 13:10
Re: New MSX1 core
Hello,
I'll look in script troubles.
Just for now, replane UCF file in Xilinx ISE (from v4 to v3) and compile.
I'll look in script troubles.
Just for now, replane UCF file in Xilinx ISE (from v4 to v3) and compile.
Sinclair escribió:Hello Fabio.fbelavenuto escribió:Source-code released:
https://github.com/fbelavenuto/msx1fpga
It's still in the beta stage!
First congratulations for your great work.
I am trying to synthesize version 3 from your GIT repository.
Through the script "_makeV3.cmd" I have the following output:
Then I tried to do it from the ZXUNO.xise file with the Xilinx tool, and I managed to generate the file that produced the previous error.Código: Seleccionar todo
D:\msx1fpga-master\synth\zxuno>_makeV3.cmd D:\msx1fpga-master\synth\zxuno>set ISEPATH=C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64 D:\msx1fpga-master\synth\zxuno>set MACHINE=zxuno_top D:\msx1fpga-master\synth\zxuno>set UCFVERSION=v3 D:\msx1fpga-master\synth\zxuno>call C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\xst -intstyle ise -ifn zxuno_top.xst -ofn zxuno_top.syr ERROR:Xst:438 - Can not open file : zxuno_top.prj Total REAL time to Xst completion: 1.00 secs Total CPU time to Xst completion: 0.98 secs --> Total memory usage is 219296 kilobytes Number of errors : 1 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) D:\msx1fpga-master\synth\zxuno>call C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc zxuno_pins_v3.ucf -p xc6slx9-tqg144- zxuno_top.ngc zxuno_top.ngd ERROR:NgdBuild:653 - An invalid target package "tqg144-" was given in the "-p" option value. Please consult the Xilinx Programmable Logic Data Book to find a legal target package. D:\msx1fpga-master\synth\zxuno>call C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\map -intstyle ise -w -ol high -mt 2 -p xc6slx9-tqg144- -logic_opt off -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -ir off -pr off -lc off -power off -o zxuno_top_map.ncd zxuno_top.ngd zxuno_top.pcf ERROR:Map:92 - NGD file "zxuno_top.ngd" not found. D:\msx1fpga-master\synth\zxuno>call C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\par -intstyle ise -w -ol high -mt 4 zxuno_top_map.ncd zxuno_top.ncd zxuno_top.pcf ERROR:Par:73 - Cannot find Input file "zxuno_top_map.ncd". Please verify that your paths and permissions are properly set for this file. D:\msx1fpga-master\synth\zxuno>call C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\trce -intstyle ise -v 3 -s -n 3 -fastpaths -xml zxuno_top.twx zxuno_top.ncd -o zxuno_top.twr zxuno_top.pcf ERROR:Portability:90 - Command line error: Argument <speed> must be specified for the switch "-s". Usage: trce.exe [-e|-v [<limit:0,2000000000>]] [-l <limit:0,2000000000>] [-n [<limit:0,2000000000>]] [-u [<limit:0,2000000000>]] [-a] [-s <speed>] [-o <report[.twr]>] [-stamp <stampfile>] [-tsi <tsifile[.tsi]>] [-xml <report[.twx]>] [-nodatasheet] [-timegroups] [-fastpaths] [-noflight] [-intstyle ise|xflow|silent] [-ise <projectfile>] [-filter <filter_file[.filter]>] <design[.ncd]> [<constraint[.pcf]>] <design[.ncd]> ... Xilinx physical design file (no default) <constraint[.pcf]> ... optional physical constraint file (default design.pcf) -o <report[.twr]> ... report output file (default design.twr) -xml <report[.twx]> ... XML report output file (default design.twx) -e [<limit>] ... produce detailed error report for timing constraints optionally limited to the number of items specified by <limit> -v [<limit>] ... produce verbose timing report for timing constraints optionally limited to the number of items specified by <limit> -l [<limit>] ... produce timing report for timing constraints optionally limited to the number of items specified by <limit> -n [<limit>] ... report paths per endpoint (default is per constraint). Limited to the number of endpoints specified by <limit>. Worst value between setup and hold is used to identify endpoint to report, using that endpoint for both setup and hold details. Use -fastpaths, to report unique endpoints for worst setup and worst hold. The -v <limit> value, dictates the number of reported paths per endpoint. This switch requries -v or -e -s <speed> ... run analysis with the speed grade specified by <speed>. This switch requries -v or -e -a ... perform advanced design analysis in the absence of a physical constraint file. This switch requires -v or -e -u [<limit>] ... report unconstrained paths optionally limited to the number of items specified by <limit>. This switch requries -v or -e -f <filename> ... use the file specified by <filename> as command input -stamp <stampfile> ... optionally generate STAMP model and data files. This switch requires -v or -e -tsi <tsifile[.tsi]> ... produce timing specification interaction report. This switch requries -v or -e -nodatasheet ... do not create the datasheet section of the report. This switch requires -v or -e -timegroups ... create the table of timegroups section of the report This switch requires -v or -e -fastpaths ... report fastest paths/verbose hold paths. This switch requires -v or -e -filter <filter_file[.filter] ... Message Filter file name (for example "filter.filter"). If specified, the contents of this file will be used to filter messages from this application. The filter file can be created using Xreport. This switch requires -v or -e -noflight ... turn off the package flight delay -intstyle <style> ... use the specified style: ise, xflow, or silent -ise <projectfile> ... use the ISE project file specified by <projectfile> TRCE: Creates a Timing Report file (TWR) derived from static timing analysis of the Physical Design file (NCD). The analysis is typically based on constraints included in the optional Physical Constraints file (PCF). D:\msx1fpga-master\synth\zxuno>call C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\bitgen -intstyle ise -f zxuno_top.ut zxuno_top.ncd ERROR:Portability:37 - Unable to open command file "zxuno_top.ut". Please make sure that this file exists and that you have read permission for it. This message may also occur if you are currently having network problems. D:\msx1fpga-master\synth\zxuno>pause Presione una tecla para continuar . . .
I re-launched _makeV3.cmd and this time the process is longer but also ends in error:
What do you claim to be the problem?Código: Seleccionar todo
D:\msx1fpga-master\synth\zxuno>_makeV3.cmd D:\msx1fpga-master\synth\zxuno>set ISEPATH=C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64 D:\msx1fpga-master\synth\zxuno>set MACHINE=zxuno_top D:\msx1fpga-master\synth\zxuno>set UCFVERSION=v3 D:\msx1fpga-master\synth\zxuno>call C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\xst -intstyle ise -ifn zxuno_top.xst -ofn zxuno_top.syr Reading design: zxuno_top.prj ========================================================================= * HDL Parsing * ========================================================================= Parsing VHDL file "D:\msx1fpga-master\synth\zxuno\ipcore_dir\pll1.vhd" into library work Parsing entity <pll1>. Parsing architecture <xilinx> of entity <pll1>. Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_pack-p.vhd" into library work Parsing package <vdp18_pack>. Parsing package body <vdp18_pack>. Parsing VHDL file "D:\msx1fpga-master\src\ram\dpram.vhd" into library work Parsing entity <dpram>. Parsing architecture <rtl> of entity <dpram>. Parsing VHDL file "D:\msx1fpga-master\src\cpu\t80_reg.vhd" into library work Parsing entity <T80_Reg>. Parsing architecture <rtl> of entity <t80_reg>. Parsing VHDL file "D:\msx1fpga-master\src\cpu\t80_pack.vhd" into library work Parsing package <T80_Pack>. Parsing VHDL file "D:\msx1fpga-master\src\cpu\t80_mcode.vhd" into library work Parsing entity <T80_MCode>. Parsing architecture <rtl> of entity <t80_mcode>. Parsing VHDL file "D:\msx1fpga-master\src\cpu\t80_alu.vhd" into library work Parsing entity <T80_ALU>. Parsing architecture <rtl> of entity <t80_alu>. Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_sprite.vhd" into library work Parsing entity <vdp18_sprite>. Parsing architecture <rtl> of entity <vdp18_sprite>. Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_pattern.vhd" into library work Parsing entity <vdp18_pattern>. Parsing architecture <rtl> of entity <vdp18_pattern>. Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_palette.vhd" into library work Parsing entity <vdp18_palette>. Parsing architecture <Memory> of entity <vdp18_palette>. Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_hor_vert.vhd" into library work Parsing entity <vdp18_hor_vert>. Parsing architecture <rtl> of entity <vdp18_hor_vert>. Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_ctrl.vhd" into library work Parsing entity <vdp18_ctrl>. Parsing architecture <rtl> of entity <vdp18_ctrl>. Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_cpuio.vhd" into library work Parsing entity <vdp18_cpuio>. Parsing architecture <rtl> of entity <vdp18_cpuio>. Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_col_mux.vhd" into library work Parsing entity <vdp18_col_mux>. Parsing architecture <rtl> of entity <vdp18_col_mux>. Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_clk_gen.vhd" into library work Parsing entity <vdp18_clk_gen>. Parsing architecture <rtl> of entity <vdp18_clk_gen>. Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_addr_mux.vhd" into library work Parsing entity <vdp18_addr_mux>. Parsing architecture <rtl> of entity <vdp18_addr_mux>. Parsing VHDL file "D:\msx1fpga-master\src\video\dblscan.vhd" into library work Parsing entity <dblscan>. Parsing architecture <rtl> of entity <dblscan>. Parsing VHDL file "D:\msx1fpga-master\src\peripheral\escci\scc_wave.vhd" into library work Parsing entity <scc_wave_mul>. Parsing architecture <rtl> of entity <scc_wave_mul>. Parsing entity <scc_wave>. Parsing architecture <Behavior> of entity <scc_wave>. Parsing VHDL file "D:\msx1fpga-master\src\cpu\t80.vhd" into library work Parsing entity <T80>. Parsing architecture <rtl> of entity <t80>. Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_core.vhd" into library work Parsing entity <vdp18_core>. Parsing architecture <struct> of entity <vdp18_core>. Parsing VHDL file "D:\msx1fpga-master\src\rom\ipl_rom.vhd" into library work Parsing entity <ipl_rom>. Parsing architecture <rtl> of entity <ipl_rom>. Parsing VHDL file "D:\msx1fpga-master\src\peripheral\swioports.vhd" into library work Parsing entity <swioports>. Parsing architecture <Behavior> of entity <swioports>. Parsing VHDL file "D:\msx1fpga-master\src\peripheral\spi.vhd" into library work Parsing entity <spi>. Parsing architecture <rtl> of entity <spi>. Parsing VHDL file "D:\msx1fpga-master\src\peripheral\romnextor.vhd" into library work Parsing entity <romnextor>. Parsing architecture <Behavior> of entity <romnextor>. Parsing VHDL file "D:\msx1fpga-master\src\peripheral\ps2_iobase.vhd" into library work Parsing entity <ps2_iobase>. Parsing architecture <rtl> of entity <ps2_iobase>. Parsing VHDL file "D:\msx1fpga-master\src\peripheral\pio.vhd" into library work Parsing entity <PIO>. Parsing architecture <Behavior> of entity <pio>. Parsing VHDL file "D:\msx1fpga-master\src\peripheral\keymap.vhd" into library work Parsing entity <keymap>. Parsing architecture <RTL> of entity <keymap>. Parsing VHDL file "D:\msx1fpga-master\src\peripheral\exp_slot.vhd" into library work Parsing entity <exp_slot>. Parsing architecture <rtl> of entity <exp_slot>. Parsing VHDL file "D:\msx1fpga-master\src\peripheral\escci\escci.vhd" into library work Parsing entity <escci>. Parsing architecture <Behavior> of entity <escci>. Parsing VHDL file "D:\msx1fpga-master\src\cpu\t80a.vhd" into library work Parsing entity <T80a>. Parsing architecture <rtl> of entity <t80a>. Parsing VHDL file "D:\msx1fpga-master\src\audio\YM2149.vhd" into library work Parsing entity <YM2149>. Parsing architecture <RTL> of entity <ym2149>. Parsing VHDL file "D:\msx1fpga-master\src\audio\dac.vhd" into library work Parsing entity <dac>. Parsing architecture <rtl> of entity <dac>. Parsing VHDL file "D:\msx1fpga-master\src\video\vdp18\vdp18_paletas_3bit_pack.vhd" into library work Parsing package <vdp18_paletas_3bit_pack>. Parsing VHDL file "D:\msx1fpga-master\src\shared\multiboot.vhd" into library work Parsing entity <multiboot>. Parsing architecture <Behavioral> of entity <multiboot>. Parsing VHDL file "D:\msx1fpga-master\src\rom\mainrom.vhd" into library work Parsing entity <mainrom>. Parsing architecture <rtl> of entity <mainrom>. Parsing VHDL file "D:\msx1fpga-master\src\ram\spram.vhd" into library work Parsing entity <spram>. Parsing architecture <rtl> of entity <spram>. Parsing VHDL file "D:\msx1fpga-master\src\peripheral\keyboard.vhd" into library work Parsing entity <keyboard>. Parsing architecture <Behavior> of entity <keyboard>. Parsing VHDL file "D:\msx1fpga-master\src\msx.vhd" into library work Parsing entity <msx>. Parsing architecture <Behavior> of entity <msx>. Parsing VHDL file "D:\msx1fpga-master\src\clocks.vhd" into library work Parsing entity <clocks>. Parsing architecture <rtl> of entity <clocks>. Parsing VHDL file "D:\msx1fpga-master\src\audio\Audio_DAC.vhd" into library work Parsing entity <Audio_DAC>. Parsing architecture <Behavior> of entity <audio_dac>. Parsing VHDL file "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" into library work Parsing entity <zxuno_top>. Parsing architecture <behavior> of entity <zxuno_top>. ========================================================================= * HDL Elaboration * ========================================================================= Elaborating entity <zxuno_top> (architecture <behavior>) from library <work>. Elaborating entity <pll1> (architecture <xilinx>) from library <work>. Elaborating entity <clocks> (architecture <rtl>) from library <work>. Elaborating entity <msx> (architecture <Behavior>) with generics from library <work>. Elaborating entity <T80a> (architecture <rtl>) with generics from library <work>. Elaborating entity <T80> (architecture <rtl>) with generics from library <work>. Elaborating entity <T80_MCode> (architecture <rtl>) with generics from library <work>. Elaborating entity <T80_ALU> (architecture <rtl>) with generics from library <work>. Elaborating entity <T80_Reg> (architecture <rtl>) from library <work>. Elaborating entity <ipl_rom> (architecture <rtl>) from library <work>. Elaborating entity <vdp18_core> (architecture <struct>) with generics from library <work>. INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_pack-p.vhd" Line 217. Case statement is complete. others clause is never selected INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_pack-p.vhd" Line 217. Case statement is complete. others clause is never selected INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_pack-p.vhd" Line 217. Case statement is complete. others clause is never selected Elaborating entity <vdp18_clk_gen> (architecture <rtl>) from library <work>. Elaborating entity <vdp18_hor_vert> (architecture <rtl>) from library <work>. Elaborating entity <vdp18_ctrl> (architecture <rtl>) from library <work>. INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_ctrl.vhd" Line 251. Case statement is complete. others clause is never selected Elaborating entity <vdp18_cpuio> (architecture <rtl>) from library <work>. INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_cpuio.vhd" Line 518. Case statement is complete. others clause is never selected INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_cpuio.vhd" Line 564. Case statement is complete. others clause is never selected INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_pack-p.vhd" Line 217. Case statement is complete. others clause is never selected INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_pack-p.vhd" Line 217. Case statement is complete. others clause is never selected INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_pack-p.vhd" Line 217. Case statement is complete. others clause is never selected INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_pack-p.vhd" Line 217. Case statement is complete. others clause is never selected INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_pack-p.vhd" Line 217. Case statement is complete. others clause is never selected Elaborating entity <vdp18_addr_mux> (architecture <rtl>) from library <work>. INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_addr_mux.vhd" Line 169. Case statement is complete. others clause is never selected Elaborating entity <vdp18_pattern> (architecture <rtl>) from library <work>. INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\video\vdp18\vdp18_pattern.vhd" Line 218. Case statement is complete. others clause is never selected Elaborating entity <vdp18_sprite> (architecture <rtl>) from library <work>. Elaborating entity <vdp18_col_mux> (architecture <rtl>) from library <work>. Elaborating entity <vdp18_palette> (architecture <Memory>) from library <work>. Elaborating entity <dblscan> (architecture <rtl>) from library <work>. Elaborating entity <dpram> (architecture <rtl>) with generics from library <work>. Elaborating entity <YM2149> (architecture <RTL>) from library <work>. INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\audio\YM2149.vhd" Line 177. Case statement is complete. others clause is never selected INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\audio\YM2149.vhd" Line 215. Case statement is complete. others clause is never selected INFO:HDLCompiler:679 - "D:\msx1fpga-master\src\audio\YM2149.vhd" Line 254. Case statement is complete. others clause is never selected Elaborating entity <PIO> (architecture <Behavior>) from library <work>. Elaborating entity <exp_slot> (architecture <rtl>) from library <work>. Elaborating entity <swioports> (architecture <Behavior>) from library <work>. Elaborating entity <spi> (architecture <rtl>) from library <work>. Elaborating entity <romnextor> (architecture <Behavior>) from library <work>. Elaborating entity <escci> (architecture <Behavior>) from library <work>. Elaborating entity <scc_wave> (architecture <Behavior>) from library <work>. Elaborating entity <dpram> (architecture <rtl>) with generics from library <work>. Elaborating entity <scc_wave_mul> (architecture <rtl>) from library <work>. Elaborating entity <mainrom> (architecture <rtl>) from library <work>. Elaborating entity <keyboard> (architecture <Behavior>) from library <work>. Elaborating entity <ps2_iobase> (architecture <rtl>) from library <work>. Elaborating entity <keymap> (architecture <RTL>) from library <work>. Elaborating entity <Audio_DAC> (architecture <Behavior>) from library <work>. Elaborating entity <dac> (architecture <rtl>) with generics from library <work>. Elaborating entity <spram> (architecture <rtl>) with generics from library <work>. Elaborating entity <multiboot> (architecture <Behavioral>) from library <work>. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit <zxuno_top>. Related source file is "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd". WARNING:Xst:647 - Input <flash_miso_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 192: Output port <clock_5m_en_o> of the instance <clks> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <bus_addr_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <bus_data_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <cnt_hor_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <cnt_ver_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <D_slots_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <ram_ce_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <ram_oe_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <rom_ce_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <rom_oe_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <bus_rd_n_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <bus_wr_n_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <bus_m1_n_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <bus_iorq_n_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <bus_mreq_n_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <bus_sltsl1_n_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <bus_sltsl2_n_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <vram_ce_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <vram_oe_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <caps_en_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <k7_motor_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <k7_audio_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <joy2_out_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <ntsc_pal_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 205: Output port <D_wait_o> of the instance <the_msx> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\syn-zxuno\zxuno_top.vhd" line 345: Output port <audio_mix_o> of the instance <audio> is unconnected or connected to loadless signal. WARNING:Xst:2935 - Signal 'flash_cs_n_o', unconnected in block 'zxuno_top', is tied to its initial value (1). WARNING:Xst:2935 - Signal 'flash_sclk_o', unconnected in block 'zxuno_top', is tied to its initial value (0). WARNING:Xst:2935 - Signal 'flash_mosi_o', unconnected in block 'zxuno_top', is tied to its initial value (0). Found 8-bit register for signal <por_cnt_s>. Found 8-bit register for signal <soft_rst_cnt_s>. Found 8-bit subtractor for signal <GND_5_o_GND_5_o_sub_2_OUT<7:0>> created at line 1308. Found 8-bit subtractor for signal <GND_5_o_GND_5_o_sub_9_OUT<7:0>> created at line 1308. Found 1-bit tristate buffer for signal <sram_data_io<7>> created at line 412 Found 1-bit tristate buffer for signal <sram_data_io<6>> created at line 412 Found 1-bit tristate buffer for signal <sram_data_io<5>> created at line 412 Found 1-bit tristate buffer for signal <sram_data_io<4>> created at line 412 Found 1-bit tristate buffer for signal <sram_data_io<3>> created at line 412 Found 1-bit tristate buffer for signal <sram_data_io<2>> created at line 412 Found 1-bit tristate buffer for signal <sram_data_io<1>> created at line 412 Found 1-bit tristate buffer for signal <sram_data_io<0>> created at line 412 Summary: inferred 2 Adder/Subtractor(s). inferred 16 D-type flip-flop(s). inferred 2 Multiplexer(s). inferred 8 Tristate(s). Unit <zxuno_top> synthesized. Synthesizing Unit <pll1>. Related source file is "D:\msx1fpga-master\synth\zxuno\ipcore_dir\pll1.vhd". Summary: no macro. Unit <pll1> synthesized. Synthesizing Unit <clocks>. Related source file is "D:\msx1fpga-master\src\clocks.vhd". Found 3-bit register for signal <clk1_cnt_q>. Found 3-bit register for signal <clk2_cnt_q>. Found 2-bit register for signal <pos_cnt3_q>. Found 2-bit register for signal <neg_cnt3_q>. Found 2-bit register for signal <sw_ff_q>. Found 1-bit register for signal <clock_5m_en_s>. Found 1-bit register for signal <clock_vdp_s>. Found 1-bit register for signal <clock_3m_s>. Found 1-bit register for signal <clock_psg_en_s>. Found 2-bit adder for signal <pos_cnt3_q[1]_GND_11_o_add_12_OUT> created at line 1241. Found 2-bit adder for signal <neg_cnt3_q[1]_GND_11_o_add_17_OUT> created at line 1241. Found 3-bit subtractor for signal <GND_11_o_GND_11_o_sub_2_OUT<2:0>> created at line 1308. Found 3-bit subtractor for signal <GND_11_o_GND_11_o_sub_8_OUT<2:0>> created at line 1308. Found 1-bit 4-to-1 multiplexer for signal <clock_cpu_o> created at line 164. Summary: inferred 4 Adder/Subtractor(s). inferred 16 D-type flip-flop(s). inferred 6 Multiplexer(s). Unit <clocks> synthesized. Synthesizing Unit <msx>. Related source file is "D:\msx1fpga-master\src\msx.vhd". hw_id_g = 8 hw_txt_g = "ZX-Uno Board" hw_version_g = "00010001" video_opt_g = 1 INFO:Xst:3210 - "D:\msx1fpga-master\src\msx.vhd" line 277: Output port <halt_n_o> of the instance <cpu> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\msx.vhd" line 277: Output port <busak_n_o> of the instance <cpu> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\msx.vhd" line 345: Output port <port_a_o> of the instance <psg> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\msx.vhd" line 345: Output port <audio_ch_a_o> of the instance <psg> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\msx.vhd" line 345: Output port <audio_ch_b_o> of the instance <psg> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\msx.vhd" line 345: Output port <audio_ch_c_o> of the instance <psg> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\msx.vhd" line 474: Output port <ram_oe_o> of the instance <escci> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\msx.vhd" line 474: Output port <ram_we_o> of the instance <escci> is unconnected or connected to loadless signal. Found 5-bit register for signal <ram_page_s>. Found 3-bit register for signal <mp_bank0_s>. Found 3-bit register for signal <mp_bank1_s>. Found 3-bit register for signal <mp_bank2_s>. Found 3-bit register for signal <mp_bank3_s>. Found 2-bit register for signal <m1_wait_ff_s>. Found 1-bit register for signal <iplram_bw_s>. Found 2-bit 4-to-1 multiplexer for signal <pslot_s> created at line 587. Found 8-bit 4-to-1 multiplexer for signal <d_from_mp_s> created at line 218. Found 3-bit 4-to-1 multiplexer for signal <mp_page_s> created at line 212. Found 1-bit tristate buffer for signal <joy1_btn1_io> created at line 518 Found 1-bit tristate buffer for signal <joy1_btn2_io> created at line 519 Found 1-bit tristate buffer for signal <joy2_btn1_io> created at line 520 Found 1-bit tristate buffer for signal <joy2_btn2_io> created at line 521 Summary: inferred 20 D-type flip-flop(s). inferred 24 Multiplexer(s). inferred 4 Tristate(s). Unit <msx> synthesized. Synthesizing Unit <T80a>. Related source file is "D:\msx1fpga-master\src\cpu\t80a.vhd". mode_g = 0 INFO:Xst:3210 - "D:\msx1fpga-master\src\cpu\t80a.vhd" line 152: Output port <IntE> of the instance <u0> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\cpu\t80a.vhd" line 152: Output port <Stop> of the instance <u0> is unconnected or connected to loadless signal. Found 1-bit register for signal <iorq_n_s>. Found 1-bit register for signal <wr_n_s>. Found 1-bit register for signal <reset_s>. Found 1-bit register for signal <req_inhibit_s>. Found 1-bit register for signal <mreq_inhibit_s>. Found 1-bit register for signal <rd_s>. Found 1-bit register for signal <mreq_s>. Found 1-bit register for signal <wait_s>. Found 8-bit register for signal <data_r>. Found 1-bit register for signal <ireq_inhibit_n_s>. Found 1-bit tristate buffer for signal <mreq_n_o> created at line 135 Found 1-bit tristate buffer for signal <iorq_n_o> created at line 136 Found 1-bit tristate buffer for signal <rd_n_o> created at line 137 Found 1-bit tristate buffer for signal <wr_n_o> created at line 138 Found 1-bit tristate buffer for signal <refresh_n_o> created at line 139 Found 1-bit tristate buffer for signal <address_o<15>> created at line 140 Found 1-bit tristate buffer for signal <address_o<14>> created at line 140 Found 1-bit tristate buffer for signal <address_o<13>> created at line 140 Found 1-bit tristate buffer for signal <address_o<12>> created at line 140 Found 1-bit tristate buffer for signal <address_o<11>> created at line 140 Found 1-bit tristate buffer for signal <address_o<10>> created at line 140 Found 1-bit tristate buffer for signal <address_o<9>> created at line 140 Found 1-bit tristate buffer for signal <address_o<8>> created at line 140 Found 1-bit tristate buffer for signal <address_o<7>> created at line 140 Found 1-bit tristate buffer for signal <address_o<6>> created at line 140 Found 1-bit tristate buffer for signal <address_o<5>> created at line 140 Found 1-bit tristate buffer for signal <address_o<4>> created at line 140 Found 1-bit tristate buffer for signal <address_o<3>> created at line 140 Found 1-bit tristate buffer for signal <address_o<2>> created at line 140 Found 1-bit tristate buffer for signal <address_o<1>> created at line 140 Found 1-bit tristate buffer for signal <address_o<0>> created at line 140 Summary: inferred 17 D-type flip-flop(s). inferred 13 Multiplexer(s). inferred 21 Tristate(s). Unit <T80a> synthesized. Synthesizing Unit <T80>. Related source file is "D:\msx1fpga-master\src\cpu\t80.vhd". Mode = 0 IOWait = 1 Flag_C = 0 Flag_N = 1 Flag_P = 2 Flag_X = 3 Flag_H = 4 Flag_Y = 5 Flag_Z = 6 Flag_S = 7 Found 1-bit register for signal <RFSH_n>. Found 1-bit register for signal <M1_n>. Found 1-bit register for signal <Alternate>. Found 1-bit register for signal <Arith16_r>. Found 1-bit register for signal <BTR_r>. Found 1-bit register for signal <Z16_r>. Found 1-bit register for signal <ALU_cpi_r>. Found 1-bit register for signal <Save_ALU_r>. Found 1-bit register for signal <PreserveC_r>. Found 1-bit register for signal <XY_Ind>. Found 1-bit register for signal <INT_s>. Found 1-bit register for signal <NMI_s>. Found 1-bit register for signal <Halt_FF>. Found 1-bit register for signal <NMICycle>. Found 1-bit register for signal <IntCycle>. Found 1-bit register for signal <IntE_FF1>. Found 1-bit register for signal <IntE_FF2>. Found 1-bit register for signal <No_BTR>. Found 1-bit register for signal <Auto_Wait_t1>. Found 1-bit register for signal <Auto_Wait_t2>. Found 16-bit register for signal <SP>. Found 8-bit register for signal <F>. Found 8-bit register for signal <Ap>. Found 8-bit register for signal <Fp>. Found 8-bit register for signal <ACC>. Found 16-bit register for signal <A>. Found 16-bit register for signal <TmpAddr>. Found 16-bit register for signal <PC>. Found 8-bit register for signal <IR>. Found 8-bit register for signal <DO>. Found 8-bit register for signal <I>. Found 8-bit register for signal <R>. Found 2-bit register for signal <ISet>. Found 2-bit register for signal <XY_State>. Found 2-bit register for signal <IStatus>. Found 3-bit register for signal <MCycles>. Found 3-bit register for signal <TState>. Found 3-bit register for signal <Pre_XY_F_M>. Found 5-bit register for signal <Read_To_Reg_r>. Found 4-bit register for signal <ALU_Op_r>. Found 3-bit register for signal <MCycle>. Found 3-bit register for signal <RegAddrA_r>. Found 3-bit register for signal <RegAddrB_r>. Found 3-bit register for signal <RegAddrC>. Found 1-bit register for signal <IncDecZ>. Found 16-bit register for signal <RegBusA_r>. Found 8-bit register for signal <BusB>. Found 8-bit register for signal <BusA>. Found 7-bit adder for signal <R[6]_GND_36_o_add_15_OUT> created at line 1241. Found 16-bit adder for signal <TmpAddr[15]_GND_36_o_add_46_OUT> created at line 1241. Found 16-bit adder for signal <PC[15]_DI_Reg[7]_add_69_OUT> created at line 568. Found 16-bit adder for signal <PC[15]_GND_36_o_add_70_OUT> created at line 1241. Found 16-bit adder for signal <RegBusC[15]_DI_Reg[7]_add_81_OUT> created at line 581. Found 16-bit adder for signal <SP[15]_GND_36_o_add_88_OUT> created at line 1241. Found 16-bit adder for signal <RegBusA[15]_GND_36_o_add_215_OUT> created at line 1253. Found 3-bit adder for signal <Pre_XY_F_M[2]_GND_36_o_add_268_OUT> created at line 1241. Found 3-bit adder for signal <MCycle[2]_GND_36_o_add_273_OUT> created at line 1241. Found 3-bit adder for signal <TState[2]_GND_36_o_add_281_OUT> created at line 1241. Found 16-bit subtractor for signal <GND_36_o_GND_36_o_sub_74_OUT<15:0>> created at line 1308. Found 16-bit subtractor for signal <GND_36_o_GND_36_o_sub_88_OUT<15:0>> created at line 1308. Found 16-bit subtractor for signal <RegBusA[15]_GND_36_o_sub_217_OUT<15:0>> created at line 1320. Found 16-bit 7-to-1 multiplexer for signal <Set_Addr_To[2]_PC[15]_wide_mux_48_OUT> created at line 487. Found 8-bit 3-to-1 multiplexer for signal <Special_LD[1]_ACC[7]_wide_mux_110_OUT> created at line 617. Found 8-bit 11-to-1 multiplexer for signal <Set_BusB_To[3]_X_35_o_wide_mux_243_OUT> created at line 863. Found 8-bit 3-to-1 multiplexer for signal <_n1475> created at line 617. Found 3-bit comparator equal for signal <T_Res> created at line 345 Found 3-bit comparator equal for signal <MCycles[2]_MCycle[2]_equal_270_o> created at line 1051 WARNING:Xst:2404 - FFs/Latches <BusReq_s<0:0>> (without init value) have a constant value of 0 in block <T80>. WARNING:Xst:2404 - FFs/Latches <BusAck<0:0>> (without init value) have a constant value of 0 in block <T80>. Summary: inferred 10 Adder/Subtractor(s). inferred 215 D-type flip-flop(s). inferred 2 Comparator(s). inferred 236 Multiplexer(s). Unit <T80> synthesized. Synthesizing Unit <T80_MCode>. Related source file is "D:\msx1fpga-master\src\cpu\t80_mcode.vhd". Mode = 0 Flag_C = 0 Flag_N = 1 Flag_P = 2 Flag_X = 3 Flag_H = 4 Flag_Y = 5 Flag_Z = 6 Flag_S = 7 WARNING:Xst:647 - Input <F<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <F<5:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit 8-to-1 multiplexer for signal <IR[5]_F[7]_Mux_192_o> created at line 174. Found 4-bit 3-to-1 multiplexer for signal <ISet[1]_IR[7]_wide_mux_506_OUT> created at line 253. Found 4-bit 3-to-1 multiplexer for signal <Set_BusA_To> created at line 253. Found 1-bit 3-to-1 multiplexer for signal <Read_To_Reg> created at line 253. Found 3-bit 3-to-1 multiplexer for signal <MCycles> created at line 253. Found 1-bit 3-to-1 multiplexer for signal <ISet[1]_IR[7]_Mux_511_o> created at line 253. Found 3-bit 3-to-1 multiplexer for signal <ISet[1]_IR[7]_wide_mux_512_OUT> created at line 253. Found 1-bit 3-to-1 multiplexer for signal <Write> created at line 253. Found 1-bit 3-to-1 multiplexer for signal <Read_To_Acc> created at line 253. Found 1-bit 3-to-1 multiplexer for signal <LDZ> created at line 253. Found 1-bit 3-to-1 multiplexer for signal <LDW> created at line 253. Found 1-bit 3-to-1 multiplexer for signal <Inc_WZ> created at line 253. Found 3-bit 3-to-1 multiplexer for signal <ISet[1]_IR[7]_wide_mux_518_OUT> created at line 253. Found 4-bit 3-to-1 multiplexer for signal <IncDec_16> created at line 253. Found 1-bit 3-to-1 multiplexer for signal <Save_ALU> created at line 253. Found 1-bit 3-to-1 multiplexer for signal <PreserveC> created at line 253. Found 4-bit 3-to-1 multiplexer for signal <ALU_Op> created at line 253. Found 1-bit 3-to-1 multiplexer for signal <Jump> created at line 253. Found 1-bit 3-to-1 multiplexer for signal <ISet[1]_IR[7]_Mux_534_o> created at line 253. Found 1-bit 3-to-1 multiplexer for signal <IORQ> created at line 253. Summary: inferred 400 Multiplexer(s). Unit <T80_MCode> synthesized. Synthesizing Unit <T80_ALU>. Related source file is "D:\msx1fpga-master\src\cpu\t80_alu.vhd". Mode = 0 Flag_C = 0 Flag_N = 1 Flag_P = 2 Flag_X = 3 Flag_H = 4 Flag_Y = 5 Flag_Z = 6 Flag_S = 7 Found 6-bit adder for signal <n0127> created at line 107. Found 5-bit adder for signal <n0126> created at line 107. Found 3-bit adder for signal <n0125> created at line 107. Found 6-bit adder for signal <n0128> created at line 107. Found 9-bit adder for signal <GND_38_o_GND_38_o_add_23_OUT> created at line 1241. Found 9-bit adder for signal <GND_38_o_GND_38_o_add_26_OUT> created at line 1241. Found 8-bit subtractor for signal <GND_38_o_GND_38_o_sub_31_OUT<7:0>> created at line 1308. Found 9-bit subtractor for signal <GND_38_o_GND_38_o_sub_34_OUT<8:0>> created at line 1308. Found 8-bit 8-to-1 multiplexer for signal <IR[5]_GND_38_o_wide_mux_44_OUT> created at line 299. Found 5-bit comparator greater for signal <GND_38_o_GND_38_o_LessThan_26_o> created at line 225 Found 4-bit comparator greater for signal <PWR_17_o_BusA[3]_LessThan_29_o> created at line 230 Found 4-bit comparator greater for signal <GND_38_o_BusA[3]_LessThan_30_o> created at line 231 Found 8-bit comparator greater for signal <PWR_17_o_BusA[7]_LessThan_33_o> created at line 236 Summary: inferred 8 Adder/Subtractor(s). inferred 4 Comparator(s). inferred 59 Multiplexer(s). Unit <T80_ALU> synthesized. Synthesizing Unit <T80_Reg>. Related source file is "D:\msx1fpga-master\src\cpu\t80_reg.vhd". Found 8x8-bit dual-port RAM <Mram_RegsH> for signal <RegsH>. Found 8x8-bit dual-port RAM <Mram_RegsL> for signal <RegsL>. Summary: inferred 4 RAM(s). Unit <T80_Reg> synthesized. Synthesizing Unit <ipl_rom>. Related source file is "D:\msx1fpga-master\src\rom\ipl_rom.vhd". Found 8-bit register for signal <data>. Found 8192x8-bit Read Only RAM for signal <addr[12]_PWR_24_o_wide_mux_0_OUT> Summary: inferred 1 RAM(s). inferred 8 D-type flip-flop(s). Unit <ipl_rom> synthesized. Synthesizing Unit <vdp18_core>. Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_core.vhd". video_opt_g = 1 INFO:Xst:3210 - "D:\msx1fpga-master\src\video\vdp18\vdp18_core.vhd" line 204: Output port <clk_en_3m58_o> of the instance <clk_gen_b> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\video\vdp18\vdp18_core.vhd" line 204: Output port <clk_en_2m68_o> of the instance <clk_gen_b> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\video\vdp18\vdp18_core.vhd" line 264: Output port <cd_oe_o> of the instance <cpu_io_b> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\video\vdp18\vdp18_core.vhd" line 264: Output port <reg_ev_o> of the instance <cpu_io_b> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\video\vdp18\vdp18_core.vhd" line 264: Output port <reg_16k_o> of the instance <cpu_io_b> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\video\vdp18\vdp18_core.vhd" line 466: Output port <oddline_o> of the instance <vo1_2.scandbl> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\video\vdp18\vdp18_core.vhd" line 466: Output port <hblank_o> of the instance <vo1_2.scandbl> is unconnected or connected to loadless signal. Found 4-bit register for signal <rgb_g_o>. Found 4-bit register for signal <rgb_b_o>. Found 4-bit register for signal <rgb_r_o>. Summary: inferred 12 D-type flip-flop(s). inferred 3 Multiplexer(s). Unit <vdp18_core> synthesized. Synthesizing Unit <vdp18_clk_gen>. Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_clk_gen.vhd". Found 4-bit register for signal <cnt_q>. Found 4-bit adder for signal <cnt_q[3]_GND_45_o_add_1_OUT> created at line 1241. Found 8x1-bit Read Only RAM for signal <cnt_q[3]_GND_45_o_Mux_5_o> Found 16x2-bit Read Only RAM for signal <_n0036> Summary: inferred 2 RAM(s). inferred 1 Adder/Subtractor(s). inferred 4 D-type flip-flop(s). inferred 4 Multiplexer(s). Unit <vdp18_clk_gen> synthesized. Synthesizing Unit <vdp18_hor_vert>. Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_hor_vert.vhd". Found 1-bit register for signal <hsync_n_o>. Found 1-bit register for signal <vsync_n_o>. Found 9-bit register for signal <cnt_hor_s>. Found 8-bit register for signal <cnt_ver_s>. Found 9-bit register for signal <cnt_hor_q>. Found 1-bit register for signal <hblank_q>. Found 1-bit register for signal <vblank_q>. Found 1-bit register for signal <cnt_vert_q<8>>. Found 1-bit register for signal <cnt_vert_q<7>>. Found 1-bit register for signal <cnt_vert_q<6>>. Found 1-bit register for signal <cnt_vert_q<5>>. Found 1-bit register for signal <cnt_vert_q<4>>. Found 1-bit register for signal <cnt_vert_q<3>>. Found 1-bit register for signal <cnt_vert_q<2>>. Found 1-bit register for signal <cnt_vert_q<1>>. Found 1-bit register for signal <cnt_vert_q<0>>. Found 9-bit adder for signal <cnt_hor_q[0]_GND_46_o_add_6_OUT> created at line 1253. Found 9-bit adder for signal <cnt_vert_q[0]_GND_46_o_add_9_OUT> created at line 1253. Found 9-bit adder for signal <first_line_s[0]_GND_46_o_add_24_OUT> created at line 1253. Found 9-bit adder for signal <cnt_hor_s[8]_GND_46_o_add_34_OUT> created at line 1241. Found 8-bit adder for signal <cnt_ver_s[7]_GND_46_o_add_37_OUT> created at line 1241. Found 9-bit comparator equal for signal <cnt_hor_q[0]_last_pix_s[0]_equal_6_o> created at line 146 Found 9-bit comparator equal for signal <cnt_vert_q[0]_last_line_s[0]_equal_9_o> created at line 153 Found 9-bit comparator not equal for signal <cnt_vert_q[0]_first_line_s[0]_equal_26_o> created at line 194 Summary: inferred 5 Adder/Subtractor(s). inferred 39 D-type flip-flop(s). inferred 3 Comparator(s). inferred 8 Multiplexer(s). Unit <vdp18_hor_vert> synthesized. Synthesizing Unit <vdp18_ctrl>. Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_ctrl.vhd". Found 1-bit register for signal <sprite_active_q>. Found 1-bit register for signal <sprite_line_act_q>. Found 1-bit register for signal <hor_active_q>. Found 1-bit register for signal <vert_active_q>. Found 1-bit register for signal <vram_ce_o>. Found 1-bit register for signal <vram_oe_o>. Found 1-bit register for signal <vram_ctrl.read_b_v>. Found 9-bit adder for signal <decode_access.num_pix_plus_6_v> created at line 1253. Found 9-bit adder for signal <n0643> created at line 1253. Found 9-bit adder for signal <n0644> created at line 1253. Found 256x9-bit Read Only RAM for signal <_n1016> Summary: inferred 1 RAM(s). inferred 3 Adder/Subtractor(s). inferred 7 D-type flip-flop(s). inferred 29 Multiplexer(s). Unit <vdp18_ctrl> synthesized. Synthesizing Unit <vdp18_cpuio>. Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_cpuio.vhd". Found 1-bit register for signal <int_n_q>. Found 8-bit register for signal <buffer_q>. Found 8-bit register for signal <tmp_q>. Found 8-bit register for signal <ctrl_reg_q<7>>. Found 8-bit register for signal <ctrl_reg_q<6>>. Found 8-bit register for signal <ctrl_reg_q<5>>. Found 8-bit register for signal <ctrl_reg_q<4>>. Found 8-bit register for signal <ctrl_reg_q<3>>. Found 8-bit register for signal <ctrl_reg_q<2>>. Found 8-bit register for signal <ctrl_reg_q<1>>. Found 8-bit register for signal <ctrl_reg_q<0>>. Found 14-bit register for signal <addr_q>. Found 4-bit register for signal <palette_idx_o>. Found 4-bit register for signal <palette_idx_s>. Found 4-bit register for signal <state_q>. Found 5-bit register for signal <sprite_5th_num_q>. Found 2-bit register for signal <cnt_v>. Found 1-bit register for signal <rdvram_sched_q>. Found 1-bit register for signal <rdvram_q>. Found 1-bit register for signal <wrvram_sched_q>. Found 1-bit register for signal <wrvram_q>. Found 1-bit register for signal <wrpal_byte2_s>. Found 1-bit register for signal <seq.write_pal_v>. Found 1-bit register for signal <status_reg_s<2>>. Found 1-bit register for signal <status_reg_s<1>>. Found 1-bit register for signal <ntsc_pal_s>. Found 1-bit register for signal <wait_o>. Found 1-bit register for signal <incr_palidx_s>. Found 16-bit register for signal <palette_val_s>. Found 1-bit register for signal <reg_if.incr_palidx_v>. Found finite state machine <FSM_0> for signal <state_q>. ----------------------------------------------------------------------- | States | 10 | | Transitions | 42 | | Inputs | 7 | | Outputs | 10 | | Clock | clock_i (rising_edge) | | Reset | reset_i (positive) | | Reset type | asynchronous | | Reset State | st_idle | | Power Up State | st_idle | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 14-bit adder for signal <addr_q[0]_GND_49_o_add_3_OUT> created at line 1241. Found 4-bit adder for signal <palette_idx_s[0]_GND_49_o_add_60_OUT> created at line 1241. Found 2-bit subtractor for signal <GND_49_o_GND_49_o_sub_159_OUT<1:0>> created at line 654. Found 8x2-bit Read Only RAM for signal <opmode_o> Found 3-bit 4-to-1 multiplexer for signal <access_ctrl.transfer_mode_v> created at line 402. WARNING:Xst:737 - Found 1-bit latch for signal <wait_s>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. Summary: inferred 1 RAM(s). inferred 3 Adder/Subtractor(s). inferred 138 D-type flip-flop(s). inferred 1 Latch(s). inferred 29 Multiplexer(s). inferred 1 Finite State Machine(s). Unit <vdp18_cpuio> synthesized. Synthesizing Unit <vdp18_addr_mux>. Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_addr_mux.vhd". WARNING:Xst:647 - Input <num_line_i<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <num_line_i<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 14-bit 3-to-1 multiplexer for signal <opmode_i[1]_GND_52_o_wide_mux_2_OUT> created at line 117. Found 14-bit 13-to-1 multiplexer for signal <vram_a_o> created at line 105. Summary: inferred 17 Multiplexer(s). Unit <vdp18_addr_mux> synthesized. Synthesizing Unit <vdp18_pattern>. Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_pattern.vhd". WARNING:Xst:647 - Input <num_line_i<1:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 8-bit register for signal <pat_name_q>. Found 8-bit register for signal <pat_tmp_q>. Found 8-bit register for signal <pat_shift_q>. Found 8-bit register for signal <pat_col_q>. Found 10-bit register for signal <pat_cnt_q>. Found 10-bit adder for signal <pat_cnt_q[0]_GND_53_o_add_0_OUT> created at line 1241. Found 10-bit subtractor for signal <GND_53_o_GND_53_o_sub_16_OUT<9:0>> created at line 1308. Found 10-bit subtractor for signal <GND_53_o_GND_53_o_sub_19_OUT<9:0>> created at line 1308. Summary: inferred 3 Adder/Subtractor(s). inferred 42 D-type flip-flop(s). inferred 19 Multiplexer(s). Unit <vdp18_pattern> synthesized. Synthesizing Unit <vdp18_sprite>. Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_sprite.vhd". Found 5-bit register for signal <sprite_numbers_q<1>>. Found 5-bit register for signal <sprite_numbers_q<2>>. Found 5-bit register for signal <sprite_numbers_q<3>>. Found 5-bit register for signal <sprite_num_q>. Found 5-bit register for signal <sprite_numbers_q<0>>. Found 3-bit register for signal <sprite_idx_q>. Found 4-bit register for signal <sprite_line_q>. Found 4-bit register for signal <sprite_cols_q<0>>. Found 4-bit register for signal <sprite_cols_q<1>>. Found 4-bit register for signal <sprite_cols_q<2>>. Found 4-bit register for signal <sprite_cols_q<3>>. Found 4-bit register for signal <sprite_ec_q>. Found 4-bit register for signal <sprite_xtog_q>. Found 8-bit register for signal <sprite_name_q>. Found 8-bit register for signal <sprite_xpos_q<0>>. Found 8-bit register for signal <sprite_xpos_q<1>>. Found 8-bit register for signal <sprite_xpos_q<2>>. Found 8-bit register for signal <sprite_xpos_q<3>>. Found 16-bit register for signal <sprite_pats_q<0>>. Found 16-bit register for signal <sprite_pats_q<1>>. Found 16-bit register for signal <sprite_pats_q<2>>. Found 16-bit register for signal <sprite_pats_q<3>>. Found 10-bit subtractor for signal <n0526> created at line 304. Found 3-bit adder for signal <sprite_idx_q[0]_GND_54_o_add_0_OUT> created at line 1241. Found 5-bit adder for signal <sprite_num_q[0]_GND_54_o_add_59_OUT> created at line 1241. Found 3-bit adder for signal <GND_54_o_GND_54_o_add_203_OUT> created at line 1241. Found 3-bit adder for signal <GND_54_o_GND_54_o_add_207_OUT> created at line 1241. Found 3-bit adder for signal <GND_54_o_GND_54_o_add_211_OUT> created at line 1241. Found 3-bit subtractor for signal <GND_54_o_GND_54_o_sub_2_OUT<2:0>> created at line 1308. Found 8-bit subtractor for signal <GND_54_o_GND_54_o_sub_8_OUT<7:0>> created at line 1308. Found 8-bit subtractor for signal <GND_54_o_GND_54_o_sub_13_OUT<7:0>> created at line 1308. Found 8-bit subtractor for signal <GND_54_o_GND_54_o_sub_18_OUT<7:0>> created at line 1308. Found 8-bit subtractor for signal <GND_54_o_GND_54_o_sub_23_OUT<7:0>> created at line 1308. Found 5-bit 4-to-1 multiplexer for signal <sprite_idx_q[1]_sprite_numbers_q[3][0]_wide_mux_216_OUT> created at line 437. Found 3-bit comparator greater for signal <GND_54_o_sprite_idx_q[0]_LessThan_4_o> created at line 151 Found 3-bit comparator greater for signal <sprite_idx_q[0]_PWR_37_o_LessThan_61_o> created at line 217 Found 9-bit comparator greater for signal <PWR_37_o_vram_d_i[0]_LessThan_181_o> created at line 299 Found 9-bit comparator lessequal for signal <n0307> created at line 311 Found 9-bit comparator greater for signal <GND_54_o_num_line_i[0]_LessThan_184_o> created at line 314 Found 9-bit comparator greater for signal <GND_54_o_num_line_i[0]_LessThan_185_o> created at line 319 Found 3-bit comparator greater for signal <spr_coll_o> created at line 426 Summary: inferred 11 Adder/Subtractor(s). inferred 160 D-type flip-flop(s). inferred 7 Comparator(s). inferred 148 Multiplexer(s). Unit <vdp18_sprite> synthesized. Synthesizing Unit <vdp18_col_mux>. Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_col_mux.vhd". Summary: inferred 7 Multiplexer(s). Unit <vdp18_col_mux> synthesized. Synthesizing Unit <vdp18_palette>. Related source file is "D:\msx1fpga-master\src\video\vdp18\vdp18_palette.vhd". Found 16-bit register for signal <ram_q<14>>. Found 16-bit register for signal <ram_q<13>>. Found 16-bit register for signal <ram_q<12>>. Found 16-bit register for signal <ram_q<11>>. Found 16-bit register for signal <ram_q<10>>. Found 16-bit register for signal <ram_q<9>>. Found 16-bit register for signal <ram_q<8>>. Found 16-bit register for signal <ram_q<7>>. Found 16-bit register for signal <ram_q<6>>. Found 16-bit register for signal <ram_q<5>>. Found 16-bit register for signal <ram_q<4>>. Found 16-bit register for signal <ram_q<3>>. Found 16-bit register for signal <ram_q<2>>. Found 16-bit register for signal <ram_q<1>>. Found 16-bit register for signal <ram_q<0>>. Found 16-bit register for signal <ram_q<15>>. Found 4-bit register for signal <read_addr_q>. INFO:Xst:3019 - HDL ADVISOR - 256 flip-flops were inferred for signal <ram_q>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. Found 16-bit 16-to-1 multiplexer for signal <data_o> created at line 102. Summary: inferred 260 D-type flip-flop(s). inferred 1 Multiplexer(s). Unit <vdp18_palette> synthesized. Synthesizing Unit <dblscan>. Related source file is "D:\msx1fpga-master\src\video\dblscan.vhd". INFO:Xst:3210 - "D:\msx1fpga-master\src\video\dblscan.vhd" line 103: Output port <data_a_o> of the instance <u_ram_a> is unconnected or connected to loadless signal. INFO:Xst:3210 - "D:\msx1fpga-master\src\video\dblscan.vhd" line 119: Output port <data_a_o> of the instance <u_ram_b> is unconnected or connected to loadless signal. Found 1-bit register for signal <vsync_n_t1_s>. Found 1-bit register for signal <ibank_s>. Found 9-bit register for signal <hpos_s>. Found 9-bit register for signal <hpos_o_s>. Found 1-bit register for signal <oddline_s>. Found 1-bit register for signal <obank_s>. Found 3-bit register for signal <vs_cnt_s>. Found 1-bit register for signal <ohs_s>. Found 1-bit register for signal <ohs_t1_s>. Found 1-bit register for signal <ovs_s>. Found 1-bit register for signal <ovs_t1_s>. Found 1-bit register for signal <hsync_n_o>. Found 1-bit register for signal <hblank_o>. Found 4-bit register for signal <col_o>. Found 1-bit register for signal <vsync_n_o>. Found 1-bit register for signal <hsync_n_t1_s>. Found 9-bit adder for signal <hpos_s[8]_GND_58_o_add_0_OUT> created at line 159. Found 9-bit adder for signal <hpos_o_s[8]_GND_58_o_add_5_OUT> created at line 176. Found 3-bit adder for signal <vs_cnt_s[2]_GND_58_o_add_7_OUT> created at line 186. Found 9-bit comparator lessequal for signal <hpos_o_s[8]_GND_58_o_LessThan_16_o> created at line 207 Found 9-bit comparator greater for signal <hpos_o_s[8]_GND_58_o_LessThan_17_o> created at line 212 Found 9-bit comparator greater for signal <PWR_42_o_hpos_o_s[8]_LessThan_18_o> created at line 212 Summary: inferred 3 Adder/Subtractor(s). inferred 37 D-type flip-flop(s). inferred 3 Comparator(s). inferred 1 Multiplexer(s). Unit <dblscan> synthesized. Synthesizing Unit <dpram_1>. Related source file is "D:\msx1fpga-master\src\ram\dpram.vhd". addr_width_g = 9 data_width_g = 4 Found 9-bit register for signal <read_addr_b_q>. Found 9-bit register for signal <read_addr_a_q>. Found 512x4-bit dual-port RAM <Mram_ram_q> for signal <ram_q>. Summary: inferred 2 RAM(s). inferred 18 D-type flip-flop(s). Unit <dpram_1> synthesized. Synthesizing Unit <YM2149>. Related source file is "D:\msx1fpga-master\src\audio\YM2149.vhd". Found 8-bit register for signal <regs_q<0>>. Found 8-bit register for signal <regs_q<1>>. Found 8-bit register for signal <regs_q<2>>. Found 8-bit register for signal <regs_q<3>>. Found 8-bit register for signal <regs_q<4>>. Found 8-bit register for signal <regs_q<5>>. Found 8-bit register for signal <regs_q<6>>. Found 8-bit register for signal <regs_q<8>>. Found 8-bit register for signal <regs_q<9>>. Found 8-bit register for signal <regs_q<10>>. Found 8-bit register for signal <regs_q<11>>. Found 8-bit register for signal <regs_q<12>>. Found 8-bit register for signal <regs_q<13>>. Found 8-bit register for signal <regs_q<14>>. Found 8-bit register for signal <regs_q<15>>. Found 8-bit register for signal <reg_addr_q>. Found 8-bit register for signal <regs_q<7>>. Found 1-bit register for signal <ena_div>. Found 1-bit register for signal <ena_div_noise>. Found 4-bit register for signal <cnt_div>. Found 1-bit register for signal <noise_div>. Found 5-bit register for signal <noise_gen_cnt>. Found 17-bit register for signal <poly17>. Found 12-bit register for signal <tone_gen_cnt<1>>. Found 12-bit register for signal <tone_gen_cnt<2>>. Found 12-bit register for signal <tone_gen_cnt<3>>. Found 3-bit register for signal <tone_gen_op>. Found 1-bit register for signal <env_ena>. Found 16-bit register for signal <env_gen_cnt>. Found 5-bit register for signal <env_vol>. Found 1-bit register for signal <env_inc>. Found 1-bit register for signal <env_hold>. Found 5-bit register for signal <A>. Found 5-bit register for signal <B>. Found 5-bit register for signal <C>. Found 8-bit register for signal <audio_ch_mix_o>. Found 8-bit register for signal <audio_ch_a_o>. Found 8-bit register for signal <audio_ch_b_o>. Found 8-bit register for signal <audio_ch_c_o>. Found 5-bit adder for signal <noise_gen_cnt[4]_GND_60_o_add_55_OUT> created at line 1241. Found 12-bit adder for signal <tone_gen_cnt[1][11]_GND_60_o_add_74_OUT> created at line 1241. Found 12-bit adder for signal <tone_gen_cnt[2][11]_GND_60_o_add_78_OUT> created at line 1241. Found 12-bit adder for signal <tone_gen_cnt[3][11]_GND_60_o_add_82_OUT> created at line 1241. Found 16-bit adder for signal <env_gen_cnt[15]_GND_60_o_add_103_OUT> created at line 1241. Found 5-bit adder for signal <env_vol[4]_GND_60_o_add_113_OUT> created at line 428. Found 5-bit adder for signal <env_vol[4]_PWR_44_o_add_114_OUT> created at line 430. Found 10-bit adder for signal <n0425> created at line 547. Found 10-bit adder for signal <n0344> created at line 547. Found 4-bit subtractor for signal <GND_60_o_GND_60_o_sub_47_OUT<3:0>> created at line 277. Found 5-bit subtractor for signal <GND_60_o_GND_60_o_sub_52_OUT<4:0>> created at line 1308. Found 12-bit subtractor for signal <GND_60_o_GND_60_o_sub_66_OUT<11:0>> created at line 1308. Found 12-bit subtractor for signal <GND_60_o_GND_60_o_sub_69_OUT<11:0>> created at line 1308. Found 12-bit subtractor for signal <GND_60_o_GND_60_o_sub_72_OUT<11:0>> created at line 1308. Found 16-bit subtractor for signal <GND_60_o_GND_60_o_sub_101_OUT<15:0>> created at line 1308. Found 8x1-bit Read Only RAM for signal <busctrl_addr_s> Found 32x8-bit Read Only RAM for signal <A[4]_A[4]_mux_153_OUT> Found 32x8-bit Read Only RAM for signal <B[4]_B[4]_mux_154_OUT> Found 32x8-bit Read Only RAM for signal <C[4]_C[4]_mux_155_OUT> Found 8-bit 16-to-1 multiplexer for signal <reg_addr_q[3]_regs_q[15][7]_wide_mux_41_OUT> created at line 229. Found 5-bit comparator greater for signal <n0070> created at line 302 Found 12-bit comparator lessequal for signal <n0092> created at line 338 Found 12-bit comparator lessequal for signal <n0100> created at line 338 Found 12-bit comparator lessequal for signal <n0108> created at line 338 Found 16-bit comparator lessequal for signal <n0128> created at line 368 Summary: inferred 4 RAM(s). inferred 14 Adder/Subtractor(s). inferred 275 D-type flip-flop(s). inferred 5 Comparator(s). inferred 25 Multiplexer(s). Unit <YM2149> synthesized. Synthesizing Unit <PIO>. Related source file is "D:\msx1fpga-master\src\peripheral\pio.vhd". Found 8-bit register for signal <portc_r>. Found 1-bit register for signal <porta_r<7>>. Found 1-bit register for signal <porta_r<6>>. Found 1-bit register for signal <porta_r<5>>. Found 1-bit register for signal <porta_r<4>>. Found 1-bit register for signal <porta_r<3>>. Found 1-bit register for signal <porta_r<2>>. Found 1-bit register for signal <porta_r<1>>. Found 1-bit register for signal <porta_r<0>>. Summary: inferred 16 D-type flip-flop(s). inferred 14 Multiplexer(s). Unit <PIO> synthesized. Synthesizing Unit <exp_slot>. Related source file is "D:\msx1fpga-master\src\peripheral\exp_slot.vhd". Found 1-bit register for signal <exp_reg_s<7>>. Found 1-bit register for signal <exp_reg_s<6>>. Found 1-bit register for signal <exp_reg_s<5>>. Found 1-bit register for signal <exp_reg_s<4>>. Found 1-bit register for signal <exp_reg_s<3>>. Found 1-bit register for signal <exp_reg_s<2>>. Found 1-bit register for signal <exp_reg_s<1>>. Found 1-bit register for signal <exp_reg_s<0>>. Found 2-bit 4-to-1 multiplexer for signal <exp_sel_s> created at line 95. Summary: inferred 8 D-type flip-flop(s). inferred 5 Multiplexer(s). Unit <exp_slot> synthesized. Synthesizing Unit <swioports>. Related source file is "D:\msx1fpga-master\src\peripheral\swioports.vhd". Found 8-bit register for signal <reg_addr_q>. Found 8-bit register for signal <maker_id_s>. Found 5-bit register for signal <index_v>. Found 2-bit register for signal <mapper_q>. Found 1-bit register for signal <turbo_on_q>. Found 1-bit register for signal <vga_en_q>. Found 1-bit register for signal <reading_v>. Found 1-bit register for signal <nextor_en_q>. Found 1-bit register for signal <softreset_q>. Found 1-bit register for signal <keymap_we_s>. Found 2-bit register for signal <turbo_on_de_v>. Found 2-bit register for signal <vga_on_de_v>. Found 10-bit register for signal <keymap_addr_q>. Found 8-bit register for signal <keymap_data_q>. Found 1-bit register for signal <keymap_we_a_v>. Found 1-bit register for signal <has_data_regv_s>. Found 8-bit register for signal <reg_data_s>. Found 10-bit adder for signal <keymap_addr_q[9]_GND_77_o_add_64_OUT> created at line 1241. Found 5-bit adder for signal <index_v[4]_GND_77_o_add_110_OUT> created at line 287. Found 8-bit 7-to-1 multiplexer for signal <_n0343> created at line 241. Found 5-bit comparator lessequal for signal <index_v[4]_GND_77_o_LessThan_110_o> created at line 286 Summary: inferred 2 Adder/Subtractor(s). inferred 61 D-type flip-flop(s). inferred 1 Comparator(s). inferred 36 Multiplexer(s). Unit <swioports> synthesized. Synthesizing Unit <spi>. Related source file is "D:\msx1fpga-master\src\peripheral\spi.vhd". Found 1-bit register for signal <spi_cs_n_o>. Found 4-bit register for signal <counter_s>. Found 8-bit register for signal <port1_r>. Found 9-bit register for signal <shift_r>. Found 1-bit register for signal <sck_delayed_s>. Found 4-bit adder for signal <counter_s[3]_GND_142_o_add_7_OUT> created at line 1241. Summary: inferred 1 Adder/Subtractor(s). inferred 23 D-type flip-flop(s). inferred 7 Multiplexer(s). Unit <spi> synthesized. Synthesizing Unit <romnextor>. Related source file is "D:\msx1fpga-master\src\peripheral\romnextor.vhd". WARNING:Xst:647 - Input <data_i<7:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 3-bit register for signal <rom_page_s>. Summary: inferred 3 D-type flip-flop(s). inferred 2 Multiplexer(s). Unit <romnextor> synthesized. Synthesizing Unit <escci>. Related source file is "D:\msx1fpga-master\src\peripheral\escci\escci.vhd". Found 8-bit register for signal <SccBank0>. Found 8-bit register for signal <SccModeA>. Found 8-bit register for signal <SccModeB>. Found 8-bit register for signal <SccBank2>. Found 8-bit register for signal <SccBank3>. Found 8-bit register for signal <SccBank1>. Found 1-bit register for signal <wav_copy_s>. Found 1-bit register for signal <flag_v>. Found 1-bit register for signal <cs_dly_s>. Found 1-bit 4-to-1 multiplexer for signal <ram_addr_o<18>> created at line 56. Found 1-bit 4-to-1 multiplexer for signal <ram_addr_o<17>> created at line 56. Found 1-bit 4-to-1 multiplexer for signal <ram_addr_o<16>> created at line 56. Found 1-bit 4-to-1 multiplexer for signal <ram_addr_o<15>> created at line 56. Found 1-bit 4-to-1 multiplexer for signal <ram_addr_o<14>> created at line 56. Found 1-bit 4-to-1 multiplexer for signal <ram_addr_o<13>> created at line 56. Found 8-bit 4-to-1 multiplexer for signal <data_o> created at line 51. Summary: inferred 51 D-type flip-flop(s). inferred 22 Multiplexer(s). Unit <escci> synthesized. Synthesizing Unit <scc_wave>. Related source file is "D:\msx1fpga-master\src\peripheral\escci\scc_wave.vhd". Found 12-bit register for signal <reg_freq_ch_a>. Found 12-bit register for signal <reg_freq_ch_b>. Found 12-bit register for signal <reg_freq_ch_c>. Found 12-bit register for signal <reg_freq_ch_d>. Found 12-bit register for signal <reg_freq_ch_e>. Found 12-bit register for signal <ff_cnt_ch_a>. Found 12-bit register for signal <ff_cnt_ch_b>. Found 12-bit register for signal <ff_cnt_ch_c>. Found 12-bit register for signal <ff_cnt_ch_d>. Found 12-bit register for signal <ff_cnt_ch_e>. Found 4-bit register for signal <reg_vol_ch_a>. Found 4-bit register for signal <reg_vol_ch_b>. Found 4-bit register for signal <reg_vol_ch_c>. Found 4-bit register for signal <reg_vol_ch_d>. Found 4-bit register for signal <reg_vol_ch_e>. Found 5-bit register for signal <reg_ch_sel>. Found 5-bit register for signal <ff_ptr_ch_a>. Found 5-bit register for signal <ff_ptr_ch_b>. Found 5-bit register for signal <ff_ptr_ch_c>. Found 5-bit register for signal <ff_ptr_ch_d>. Found 5-bit register for signal <ff_ptr_ch_e>. Found 8-bit register for signal <reg_mode_sel>. Found 8-bit register for signal <ff_wave_dat>. Found 3-bit register for signal <ff_ch_num_dl>. Found 3-bit register for signal <ff_ch_num>. Found 15-bit register for signal <ff_mix>. Found 15-bit register for signal <ff_wave>. Found 1-bit register for signal <ff_rst_ch_a>. Found 1-bit register for signal <ff_rst_ch_b>. Found 1-bit register for signal <ff_rst_ch_c>. Found 1-bit register for signal <ff_rst_ch_d>. Found 1-bit register for signal <ff_rst_ch_e>. Found 1-bit register for signal <ff_req_dl>. Found 5-bit adder for signal <ff_ptr_ch_a[4]_GND_146_o_add_47_OUT> created at line 244. Found 5-bit adder for signal <ff_ptr_ch_b[4]_GND_146_o_add_55_OUT> created at line 254. Found 5-bit adder for signal <ff_ptr_ch_c[4]_GND_146_o_add_63_OUT> created at line 264. Found 5-bit adder for signal <ff_ptr_ch_d[4]_GND_146_o_add_71_OUT> created at line 274. Found 5-bit adder for signal <ff_ptr_ch_e[4]_GND_146_o_add_79_OUT> created at line 284. Found 3-bit adder for signal <ff_ch_num[2]_GND_146_o_add_120_OUT> created at line 379. Found 15-bit adder for signal <w_mul[11]_ff_mix[14]_add_124_OUT> created at line 393. Found 12-bit subtractor for signal <GND_146_o_GND_146_o_sub_49_OUT<11:0>> created at line 247. Found 12-bit subtractor for signal <GND_146_o_GND_146_o_sub_57_OUT<11:0>> created at line 257. Found 12-bit subtractor for signal <GND_146_o_GND_146_o_sub_65_OUT<11:0>> created at line 267. Found 12-bit subtractor for signal <GND_146_o_GND_146_o_sub_73_OUT<11:0>> created at line 277. Found 12-bit subtractor for signal <GND_146_o_GND_146_o_sub_81_OUT<11:0>> created at line 287. Found 8x5-bit Read Only RAM for signal <w_ch_dec> Found 4-bit 7-to-1 multiplexer for signal <w_ch_vol> created at line 337. Found 8-bit 4-to-1 multiplexer for signal <_n0386> created at line 82. Found 8-bit comparator greater for signal <addr_i[7]_PWR_105_o_LessThan_1_o> created at line 143 Summary: inferred 1 RAM(s). inferred 12 Adder/Subtractor(s). inferred 228 D-type flip-flop(s). inferred 1 Comparator(s). inferred 31 Multiplexer(s). Unit <scc_wave> synthesized. Synthesizing Unit <dpram_2>. Related source file is "D:\msx1fpga-master\src\ram\dpram.vhd". addr_width_g = 8 data_width_g = 8 Found 8-bit register for signal <read_addr_b_q>. Found 8-bit register for signal <read_addr_a_q>. Found 256x8-bit dual-port RAM <Mram_ram_q> for signal <ram_q>. Summary: inferred 2 RAM(s). inferred 16 D-type flip-flop(s). Unit <dpram_2> synthesized. Synthesizing Unit <scc_wave_mul>. Related source file is "D:\msx1fpga-master\src\peripheral\escci\scc_wave.vhd". Found 8x5-bit multiplier for signal <w_mul> created at line 52. Summary: inferred 1 Multiplier(s). Unit <scc_wave_mul> synthesized. Synthesizing Unit <mainrom>. Related source file is "D:\msx1fpga-master\src\rom\mainrom.vhd". Found 8-bit register for signal <data>. Found 32768x8-bit Read Only RAM for signal <addr[14]_GND_160_o_wide_mux_0_OUT> Summary: inferred 1 RAM(s). inferred 8 D-type flip-flop(s). Unit <mainrom> synthesized. Synthesizing Unit <keyboard>. Related source file is "D:\msx1fpga-master\src\peripheral\keyboard.vhd". Found 8-bit register for signal <cols_o>. Found 4-bit register for signal <extra_keys_s>. Found 3-bit register for signal <skip_count_v>. Found 3-bit register for signal <keymap_seq_s>. Found 2-bit register for signal <extended_v>. Found 2-bit register for signal <extended_s>. Found 8-bit register for signal <matrix_s<15>>. Found 8-bit register for signal <matrix_s<14>>. Found 8-bit register for signal <matrix_s<13>>. Found 8-bit register for signal <matrix_s<12>>. Found 8-bit register for signal <matrix_s<11>>. Found 8-bit register for signal <matrix_s<10>>. Found 8-bit register for signal <matrix_s<9>>. Found 8-bit register for signal <matrix_s<8>>. Found 8-bit register for signal <matrix_s<7>>. Found 8-bit register for signal <matrix_s<6>>. Found 8-bit register for signal <matrix_s<5>>. Found 8-bit register for signal <matrix_s<4>>. Found 8-bit register for signal <matrix_s<3>>. Found 8-bit register for signal <matrix_s<2>>. Found 8-bit register for signal <matrix_s<1>>. Found 8-bit register for signal <matrix_s<0>>. Found 10-bit register for signal <keymap_addr_s>. Found 1-bit register for signal <reset_o>. Found 1-bit register for signal <por_o>. Found 1-bit register for signal <ed_resp_v>. Found 1-bit register for signal <break_v>. Found 1-bit register for signal <shift_v>. Found 1-bit register for signal <ctrl_v>. Found 1-bit register for signal <alt_v>. Found 1-bit register for signal <has_keycode_s>. Found 1-bit register for signal <break_s>. Found 1-bit register for signal <shift_s>. Found 1-bit register for signal <reload_core_o>. Found 1-bit register for signal <data_load_s>. Found 1-bit register for signal <batcode_v>. Found 8-bit register for signal <d_to_send_s>. Found 1-bit register for signal <led_caps_v>. Found 4-bit register for signal <row_v>. Found 3-bit register for signal <col_v>. Found 1-bit register for signal <mod_shift_v>. Found finite state machine <FSM_1> for signal <keymap_seq_s>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 6 | | Inputs | 1 | | Outputs | 3 | | Clock | clock_i (rising_edge) | | Reset | reset_i (positive) | | Reset type | asynchronous | | Reset State | km_idle | | Power Up State | km_idle | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_2> for signal <extended_v>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 35 | | Inputs | 10 | | Outputs | 5 | | Clock | clock_i (rising_edge) | | Reset | reset_i (positive) | | Reset type | asynchronous | | Reset State | 00 | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 3-bit subtractor for signal <GND_161_o_GND_161_o_sub_4_OUT<2:0>> created at line 161. Found 8-bit 16-to-1 multiplexer for signal <rows_coded_i[3]_matrix_s[15][7]_wide_mux_71_OUT> created at line 255. Summary: inferred 1 Adder/Subtractor(s). inferred 185 D-type flip-flop(s). inferred 162 Multiplexer(s). inferred 2 Finite State Machine(s). Unit <keyboard> synthesized. Synthesizing Unit <ps2_iobase>. Related source file is "D:\msx1fpga-master\src\peripheral\ps2_iobase.vhd". Found 2-bit register for signal <dat_sync_v>. Found 2-bit register for signal <clk_sync_v>. Found 16-bit register for signal <edge_detect_v>. Found 8-bit register for signal <sdata_s>. Found 1-bit register for signal <data_rdy_o>. Found 4-bit register for signal <_v4>. Found 16-bit register for signal <timeout_q>. Found 1-bit register for signal <sigsending_s>. Found 8-bit register for signal <hdata_s>. Found 1-bit register for signal <sigclkreleased>. Found 1-bit register for signal <sigclkheld>. Found 9-bit register for signal <count_v>. Found 1-bit register for signal <count_v[8]_clock_i_DFF_220>. Found 1-bit register for signal <ps2_data_io_clock_i_DFF_221_q>. Found 1-bit register for signal <sigsendend_s>. Found 4-bit register for signal <TOPS2.count_v>. Found 1-bit register for signal <ps2_clk_io_clock_i_DFF_217_q>. Found 1-bit register for signal <PWR_128_o_clock_i_DFF_223>. Found 4-bit adder for signal <count_v[3]_GND_162_o_add_12_OUT> created at line 117. Found 16-bit adder for signal <timeout_q[15]_GND_162_o_add_18_OUT> created at line 1241. Found 9-bit adder for signal <count_v[8]_GND_162_o_add_36_OUT> created at line 169. Found 4-bit adder for signal <TOPS2.count_v[3]_GND_162_o_add_48_OUT> created at line 216. Found 3-bit subtractor for signal <GND_162_o_GND_162_o_sub_9_OUT<2:0>> created at line 110. Found 1-bit 8-to-1 multiplexer for signal <TOPS2.count_v[2]_hdata_s[7]_Mux_43_o> created at line 200. Found 1-bit tristate buffer for signal <ps2_clk_io> created at line 152 Found 1-bit tristate buffer for signal <ps2_data_io> created at line 184 Found 4-bit comparator lessequal for signal <count_v[3]_PWR_128_o_LessThan_8_o> created at line 109 Found 9-bit comparator greater for signal <count_v[8]_PWR_128_o_LessThan_34_o> created at line 163 Found 9-bit comparator greater for signal <count_v[8]_PWR_128_o_LessThan_36_o> created at line 168 Found 4-bit comparator greater for signal <TOPS2.count_v[3]_PWR_128_o_LessThan_43_o> created at line 199 Summary: inferred 5 Adder/Subtractor(s). inferred 78 D-type flip-flop(s). inferred 4 Comparator(s). inferred 21 Multiplexer(s). inferred 2 Tristate(s). Unit <ps2_iobase> synthesized. Synthesizing Unit <keymap>. Related source file is "D:\msx1fpga-master\src\peripheral\keymap.vhd". Found 1024x8-bit dual-port RAM <Mram_ram_q> for signal <ram_q>. Found 10-bit register for signal <read_addr_q>. Summary: inferred 1 RAM(s). inferred 10 D-type flip-flop(s). Unit <keymap> synthesized. . . . . . . . . . All constraints were met. Generating Pad Report. All signals are completely routed. WARNING:Par:283 - There are 3 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. Total REAL time to PAR completion: 54 secs Total CPU time to PAR completion (all processors): 1 mins 2 secs Peak Memory Usage: 420 MB Placer: Placement generated during map. Routing: Completed - No errors found. Timing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 5 Number of info messages: 0 Writing design to file zxuno_top.ncd PAR done! D:\msx1fpga-master\synth\zxuno>call C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\trce -intstyle ise -v 3 -s -n 3 -fastpaths -xml zxuno_top.twx zxuno_top.ncd -o zxuno_top.twr zxuno_top.pcf ERROR:Portability:90 - Command line error: Argument <speed> must be specified for the switch "-s". Usage: trce.exe [-e|-v [<limit:0,2000000000>]] [-l <limit:0,2000000000>] [-n [<limit:0,2000000000>]] [-u [<limit:0,2000000000>]] [-a] [-s <speed>] [-o <report[.twr]>] [-stamp <stampfile>] [-tsi <tsifile[.tsi]>] [-xml <report[.twx]>] [-nodatasheet] [-timegroups] [-fastpaths] [-noflight] [-intstyle ise|xflow|silent] [-ise <projectfile>] [-filter <filter_file[.filter]>] <design[.ncd]> [<constraint[.pcf]>] <design[.ncd]> ... Xilinx physical design file (no default) <constraint[.pcf]> ... optional physical constraint file (default design.pcf) -o <report[.twr]> ... report output file (default design.twr) -xml <report[.twx]> ... XML report output file (default design.twx) -e [<limit>] ... produce detailed error report for timing constraints optionally limited to the number of items specified by <limit> -v [<limit>] ... produce verbose timing report for timing constraints optionally limited to the number of items specified by <limit> -l [<limit>] ... produce timing report for timing constraints optionally limited to the number of items specified by <limit> -n [<limit>] ... report paths per endpoint (default is per constraint). Limited to the number of endpoints specified by <limit>. Worst value between setup and hold is used to identify endpoint to report, using that endpoint for both setup and hold details. Use -fastpaths, to report unique endpoints for worst setup and worst hold. The -v <limit> value, dictates the number of reported paths per endpoint. This switch requries -v or -e -s <speed> ... run analysis with the speed grade specified by <speed>. This switch requries -v or -e -a ... perform advanced design analysis in the absence of a physical constraint file. This switch requires -v or -e -u [<limit>] ... report unconstrained paths optionally limited to the number of items specified by <limit>. This switch requries -v or -e -f <filename> ... use the file specified by <filename> as command input -stamp <stampfile> ... optionally generate STAMP model and data files. This switch requires -v or -e -tsi <tsifile[.tsi]> ... produce timing specification interaction report. This switch requries -v or -e -nodatasheet ... do not create the datasheet section of the report. This switch requires -v or -e -timegroups ... create the table of timegroups section of the report This switch requires -v or -e -fastpaths ... report fastest paths/verbose hold paths. This switch requires -v or -e -filter <filter_file[.filter] ... Message Filter file name (for example "filter.filter"). If specified, the contents of this file will be used to filter messages from this application. The filter file can be created using Xreport. This switch requires -v or -e -noflight ... turn off the package flight delay -intstyle <style> ... use the specified style: ise, xflow, or silent -ise <projectfile> ... use the ISE project file specified by <projectfile> TRCE: Creates a Timing Report file (TWR) derived from static timing analysis of the Physical Design file (NCD). The analysis is typically based on constraints included in the optional Physical Constraints file (PCF). D:\msx1fpga-master\synth\zxuno>call C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\bitgen -intstyle ise -f zxuno_top.ut zxuno_top.ncd WARNING:Bitgen:300 - The ConfigRate:2 setting will be ignored because the ExtMasterCclk_en option has been set to Yes. INFO:Bitgen:341 - This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, requires a special bit stream format. For more information, please reference Xilinx Answer Record 39999. WARNING:PhysDesignRules:372 - Gated clock. Clock net the_msx/pio/reset_i_GND_73_o_AND_297_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net the_msx/vdp/hor_vert_b/reset_i_first_line_s[2]_AND_118_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net the_msx/vdp/hor_vert_b/reset_i_first_line_s[2]_AND_117_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net por_clock_s is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net the_msx/swiop/clock_i_inv is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net clks/clock_out1_s is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net keyb/ps2_port/sigclkheld_enable_i_AND_641_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net the_msx/psg/Mram_busctrl_addr_s is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net the_msx/exp/sltsl_n_i_ffff_s_OR_233_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net the_msx/vdp/cpu_io_b/mode_i[0]_wrvram_q_Mux_125_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:367 - The signal <the_msx/cpu/u0/Regs/Mram_RegsH11_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal <the_msx/cpu/u0/Regs/Mram_RegsL11_RAMD_D1_O> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer Record 39999. D:\msx1fpga-master\synth\zxuno>pause Presione una tecla para continuar . . . D:\msx1fpga-master\synth\zxuno>
I would love to run your great work on my ZX-ONE V2.
Thank you very much.
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- Mensajes: 100
- Registrado: 08 Sep 2016, 13:10
Re: New MSX1 core
Hi Antonio,
HDMI works in Victor Multicore Board (made only in Brazil). I have not yet ported to ZX-Uno Board, but it's easy.
Thanks.
HDMI works in Victor Multicore Board (made only in Brazil). I have not yet ported to ZX-Uno Board, but it's easy.
Thanks.
antoniovillena escribió:I think Fabio support both v3 and v4 versions of ZX-Uno. If send him a tested zxuno_pins_v2.ucf he can put in this folder:
https://github.com/fbelavenuto/msx1fpga ... ynth/zxuno
Fabio, browsing into the repository I've found a comment "HDMI works!". I will test in the future with the HDMI-ESP12 addon. If works I'll send you an addon for free. A guy in the forum (yombo) has ordered yesterday a batch with the new version. It will take a month.
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- Mensajes: 100
- Registrado: 08 Sep 2016, 13:10
Re: New MSX1 core
Hum, very thanks, I'll add the file.
Sinclair escribió:I have tested it with a zxuno_pins_v2.ucf adapted from the v4 by me and it still fails in the same thing.antoniovillena escribió:I think Fabio support both v3 and v4 versions of ZX-Uno. If send him a tested zxuno_pins_v2.ucf he can put in this folder:
https://github.com/fbelavenuto/msx1fpga ... ynth/zxuno.
If you want, yourselft can try it.
zxuno_pins_v2.ucfEDIT:Código: Seleccionar todo
# Clocks NET "clock_50_i" LOC="P55" | IOSTANDARD = LVCMOS33; # Video output NET "vga_r_o<2>" LOC="P93" | IOSTANDARD = LVCMOS33; NET "vga_r_o<1>" LOC="P92" | IOSTANDARD = LVCMOS33; NET "vga_r_o<0>" LOC="P88" | IOSTANDARD = LVCMOS33; NET "vga_g_o<2>" LOC="P84" | IOSTANDARD = LVCMOS33; NET "vga_g_o<1>" LOC="P83" | IOSTANDARD = LVCMOS33; NET "vga_g_o<0>" LOC="P82" | IOSTANDARD = LVCMOS33; NET "vga_b_o<2>" LOC="P81" | IOSTANDARD = LVCMOS33; NET "vga_b_o<1>" LOC="P80" | IOSTANDARD = LVCMOS33; NET "vga_b_o<0>" LOC="P79" | IOSTANDARD = LVCMOS33; NET "vga_csync_n_o" LOC="P87" | IOSTANDARD = LVCMOS33; NET "vga_vsync_n_o" LOC="P85" | IOSTANDARD = LVCMOS33; NET "vga_ntsc_o" LOC="P67" | IOSTANDARD = LVCMOS33; NET "vga_pal_o" LOC="P66" | IOSTANDARD = LVCMOS33; # Sound input/output NET "dac_l_o" LOC="P8" | IOSTANDARD = LVCMOS33; NET "dac_r_o" LOC="P9" | IOSTANDARD = LVCMOS33; NET "ear_i" LOC="P105" | IOSTANDARD = LVCMOS33; # SRAM NET "sram_addr_o<0>" LOC="P115" | IOSTANDARD = LVCMOS33; NET "sram_addr_o<1>" LOC="P116" | IOSTANDARD = LVCMOS33; NET "sram_addr_o<2>" LOC="P117" | IOSTANDARD = LVCMOS33; NET "sram_addr_o<3>" LOC="P119" | IOSTANDARD = LVCMOS33; NET "sram_addr_o<4>" LOC="P120" | IOSTANDARD = LVCMOS33; NET "sram_addr_o<5>" LOC="P123" | IOSTANDARD = LVCMOS33; NET "sram_addr_o<6>" LOC="P126" | IOSTANDARD = LVCMOS33; NET "sram_addr_o<7>" LOC="P131" | IOSTANDARD = LVCMOS33; NET "sram_addr_o<8>" LOC="P127" | IOSTANDARD = LVCMOS33; NET "sram_addr_o<9>" LOC="P124" | IOSTANDARD = LVCMOS33; NET "sram_addr_o<10>" LOC="P118" | IOSTANDARD = LVCMOS33; NET "sram_addr_o<11>" LOC="P121" | IOSTANDARD = LVCMOS33; NET "sram_addr_o<12>" LOC="P133" | IOSTANDARD = LVCMOS33; NET "sram_addr_o<13>" LOC="P132" | IOSTANDARD = LVCMOS33; NET "sram_addr_o<14>" LOC="P137" | IOSTANDARD = LVCMOS33; NET "sram_addr_o<15>" LOC="P140" | IOSTANDARD = LVCMOS33; NET "sram_addr_o<16>" LOC="P139" | IOSTANDARD = LVCMOS33; NET "sram_addr_o<17>" LOC="P141" | IOSTANDARD = LVCMOS33; NET "sram_addr_o<18>" LOC="P138" | IOSTANDARD = LVCMOS33; #NET "sram_addr_o<19>" LOC="P" | IOSTANDARD = LVCMOS33; #NET "sram_addr_o<20>" LOC="P" | IOSTANDARD = LVCMOS33; NET "sram_data_io<0>" LOC="P114" | IOSTANDARD = LVCMOS33; NET "sram_data_io<1>" LOC="P112" | IOSTANDARD = LVCMOS33; NET "sram_data_io<2>" LOC="P111" | IOSTANDARD = LVCMOS33; NET "sram_data_io<3>" LOC="P99" | IOSTANDARD = LVCMOS33; NET "sram_data_io<4>" LOC="P100" | IOSTANDARD = LVCMOS33; NET "sram_data_io<5>" LOC="P101" | IOSTANDARD = LVCMOS33; NET "sram_data_io<6>" LOC="P102" | IOSTANDARD = LVCMOS33; NET "sram_data_io<7>" LOC="P104" | IOSTANDARD = LVCMOS33; NET "sram_we_n_o" LOC="P134" | IOSTANDARD = LVCMOS33; # Keyboard NET "ps2_clk_io" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP; NET "ps2_data_io" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "ps2_mouse_clk_io" LOC="P94" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "ps2_mouse_data_io" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP; # SD/MMC NET "sd_cs_n_o" LOC="P59" | IOSTANDARD = LVCMOS33; NET "sd_sclk_o" LOC="P75" | IOSTANDARD = LVCMOS33; NET "sd_mosi_o" LOC="P74" | IOSTANDARD = LVCMOS33; NET "sd_miso_i" LOC="P78" | IOSTANDARD = LVCMOS33; # SPI Flash NET "flash_cs_n_o" LOC="P38" | IOSTANDARD = LVCMOS33; NET "flash_sclk_o" LOC="P70" | IOSTANDARD = LVCMOS33; NET "flash_mosi_o" LOC="P64" | IOSTANDARD = LVCMOS33; NET "flash_miso_i" LOC="P65" | IOSTANDARD = LVCMOS33; #NET "flash_wp_o" LOC="P62" | IOSTANDARD = LVCMOS33; #NET "flash_hold_o" LOC="P61" | IOSTANDARD = LVCMOS33; # Joystick NET "joy_up_i" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP; NET "joy_down_i" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP; NET "joy_left_i" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP; NET "joy_right_i" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP; NET "joy_fire1_i" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP; NET "joy_fire2_i" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP; NET "joy_fire3_o" LOC="P7" | IOSTANDARD = LVCMOS33; # GPIO NET "joy2_btn1_io" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP; # GPIO 6 NET "joy2_btn2_io" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP; # GPIO 7 #NET "gpio_io<6>" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<7>" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<8>" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<9>" LOC="P51" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<10>" LOC="P50" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<11>" LOC="P48" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<12>" LOC="P47" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<13>" LOC="P46" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<14>" LOC="P45" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<15>" LOC="P44" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<16>" LOC="P43" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<17>" LOC="P41" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<18>" LOC="P40" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<19>" LOC="P35" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<20>" LOC="P34" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<21>" LOC="P33" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<22>" LOC="P32" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<23>" LOC="P30" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<24>" LOC="P29" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<25>" LOC="P27" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<26>" LOC="P26" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<27>" LOC="P24" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<28>" LOC="P23" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<29>" LOC="P22" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<30>" LOC="P21" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<31>" LOC="P17" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<32>" LOC="P16" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<33>" LOC="P15" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<34>" LOC="P14" | IOSTANDARD = LVCMOS33 | PULLUP; #NET "gpio_io<35>" LOC="P12" | IOSTANDARD = LVCMOS33 | PULLUP; # DEBUG NET "led_o" LOC="P10" | IOSTANDARD = LVCMOS33; # Clock Constraints NET "clock_50_i" TNM_NET = clock_50_i; TIMESPEC TS_clock_50_i = PERIOD "clock_50_i" 20 ns HIGH 50%; NET "clock_master_s" TNM_NET = clock_master_s; TIMESPEC TS_clock_master_s = PERIOD "clock_master_s" 46.56 ns HIGH 50%; NET "clks/clock_3m_s" TNM_NET = clks/clock_3m_s; TIMESPEC TS_clks_clock_3m_s = PERIOD "clks/clock_3m_s" 279.365 ns HIGH 50%; NET "clks/clock_vdp_s" TNM_NET = clks/clock_vdp_s; TIMESPEC TS_clks_clock_vdp_s = PERIOD "clks/clock_vdp_s" 93.121 ns HIGH 50%;
Fixed!
Confirmed that it works correctly on my ZX-UNO V2.
Fabio, can you add this file to your repository if you want.
- antoniovillena
- Mensajes: 2621
- Registrado: 27 Sep 2015, 20:41
Re: New MSX1 core
If you want, send me a PM with your address and I'll send a v1 HDMI addon to Brazil.
fbelavenuto escribió:Hi Antonio,
HDMI works in Victor Multicore Board (made only in Brazil). I have not yet ported to ZX-Uno Board, but it's easy.
Thanks.