ZX-Uno running on Next board (WIP)

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brunosilva
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ZX-Uno running on Next board (WIP)

Mensajepor brunosilva » 17 Dic 2017, 15:36

Hi

so I already received the next board and the zxuno firmware and a zxspectrum core is running in a beta stage :)

you must have a jtag to read the backup (you should) and write the new MCS file (in attach) - Antonio send me to test (its easy to do this with Impact).

Also the next core (that is present in 0.4 version) - we already have the 0.5 as I write this post - is in attach (you need also to copy the files from 0.4 to a memory card) - also Antonio send me to test.

ucf file here: https://www.specnext.com/forum/viewtopic.php?f=6&t=885

my board hasn't (yet - hope to get this in the first week of january) the upgrades (rtc, more memory, internal speaker, rp0, wifi) so i cannot test any of this.

for now, this doesn't work:
- internal keyboard (ps2 works fine)
- buttons: nmi, reset,etc (next have reset, m1 and drive)
- hdmi (only works with vga)

also image (in my case with an Asus monitor the image has some, I don't know how to say, ghost, vertical stuff hapening :) and so on - it's not clean as is next core).

I don't have coding skills but I can test cores and stuff.

Also the fpga is bigger and its possible to improve the existing cores with more stuff :)

More technical questions maybe Antonio can answer :)

Thanks all that can help port cores and improve zxuno in next board :)

Bruno
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antoniovillena
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Re: ZX-Uno running on Next board (WIP)

Mensajepor antoniovillena » 17 Dic 2017, 16:51

For upgrade the Next core just remove the first 512 bytes of the TBBLUE.TBU file and rename to CORE2.ZX2. Here is an utility to do this.
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fromNextToZxuno.zip
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ZX-Uno · Clon de ordenador ZX Spectrum basado en FPGA

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Re: ZX-Uno running on Next board (WIP)

Mensajepor antoniovillena » 17 Dic 2017, 16:53

The ucf file for the ZX-Uno core adapted to the TBBlue is here:

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# Clocks & debug
NET "clk50mhz"        LOC="T8"  | IOSTANDARD = LVCMOS33;
NET "testled"         IOSTANDARD = LVCMOS33;

# Video output
NET "r<2>"            LOC="H5"   | IOSTANDARD = LVCMOS33;
NET "r<1>"            LOC="H3"   | IOSTANDARD = LVCMOS33;
NET "r<0>"            LOC="H4"   | IOSTANDARD = LVCMOS33;
#NET "rl<2>"           LOC="H1"   | IOSTANDARD = LVCMOS33;
#NET "rl<1>"           LOC="K1"   | IOSTANDARD = LVCMOS33;
#NET "rl<0>"           LOC="K2"   | IOSTANDARD = LVCMOS33;
NET "g<2>"            LOC="G3"   | IOSTANDARD = LVCMOS33;
NET "g<1>"            LOC="F3"   | IOSTANDARD = LVCMOS33;
NET "g<0>"            LOC="F4"   | IOSTANDARD = LVCMOS33;
#NET "gl<2>"           LOC="M1"   | IOSTANDARD = LVCMOS33;
#NET "gl<1>"           LOC="P1"   | IOSTANDARD = LVCMOS33;
#NET "gl<0>"           LOC="P2"   | IOSTANDARD = LVCMOS33;
NET "b<2>"            LOC="H1"   | IOSTANDARD = LVCMOS33;
NET "b<1>"            LOC="C2"   | IOSTANDARD = LVCMOS33;
NET "b<0>"            LOC="B1"   | IOSTANDARD = LVCMOS33;
#NET "bl<2>"           LOC="E4"   | IOSTANDARD = LVCMOS33;
#NET "bl<1>"           LOC="F3"   | IOSTANDARD = LVCMOS33;
#NET "bl<0>"           LOC="F4"   | IOSTANDARD = LVCMOS33;
NET "hsync"           LOC="B10"   | IOSTANDARD = LVCMOS33;
NET "vsync"           LOC="A11"   | IOSTANDARD = LVCMOS33;
NET "stdn"            IOSTANDARD = LVCMOS33;
NET "stdnb"           IOSTANDARD = LVCMOS33;

# Sound input/output
NET "audio_out_left"  LOC="B2"   | IOSTANDARD = LVCMOS33;
NET "audio_out_right" LOC="A2"   | IOSTANDARD = LVCMOS33;
NET "ear"             LOC="A3"   | IOSTANDARD = LVCMOS33;

# Keyboard and mouse
NET "clkps2"          LOC="K3"  | IOSTANDARD = LVCMOS33 | PULLUP;
NET "dataps2"         LOC="J3"  | IOSTANDARD = LVCMOS33 | PULLUP;
NET "mouseclk"        LOC="K6"  | IOSTANDARD = LVCMOS33 | PULLUP;
NET "mousedata"       LOC="J4"  | IOSTANDARD = LVCMOS33 | PULLUP;

# SRAM
NET "sram_addr<0>"    LOC="M2"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<1>"    LOC="M1"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<2>"    LOC="N1"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<3>"    LOC="P2"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<4>"    LOC="P1"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<5>"    LOC="L3"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<6>"    LOC="M4"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<7>"    LOC="M3"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<8>"    LOC="N4"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<9>"    LOC="N3"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<10>"   LOC="C4"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<11>"   LOC="C3"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<12>"   LOC="D3"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<13>"   LOC="E4"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<14>"   LOC="E3"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<15>"   LOC="F2"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<16>"   LOC="F1"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<17>"   LOC="G1"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<18>"   LOC="H2"  | IOSTANDARD = LVCMOS33;
NET "sram_addr<19>"   IOSTANDARD = LVCMOS33;
NET "sram_addr<20>"   IOSTANDARD = LVCMOS33;

NET "sram_data<0>"    LOC="J6"  | IOSTANDARD = LVCMOS33;
NET "sram_data<1>"    LOC="L5"  | IOSTANDARD = LVCMOS33;
NET "sram_data<2>"    LOC="K5"  | IOSTANDARD = LVCMOS33;
NET "sram_data<3>"    LOC="M6"  | IOSTANDARD = LVCMOS33;
NET "sram_data<4>"    LOC="P4"  | IOSTANDARD = LVCMOS33;
NET "sram_data<5>"    LOC="R3"  | IOSTANDARD = LVCMOS33;
NET "sram_data<6>"    LOC="T4"  | IOSTANDARD = LVCMOS33;
NET "sram_data<7>"    LOC="N6"  | IOSTANDARD = LVCMOS33;

NET "sram_we_n"       LOC="M5"  | IOSTANDARD = LVCMOS33;
NET "sram_ce_n"       LOC="R2"  | IOSTANDARD = LVCMOS33;
NET "sram_oe_n"       LOC="E1"  | IOSTANDARD = LVCMOS33;

# SPI Flash
NET "flash_cs_n"      LOC="T3"   | IOSTANDARD = LVCMOS33;
NET "flash_clk"       LOC="R11"  | IOSTANDARD = LVCMOS33;
NET "flash_mosi"      LOC="T10"  | IOSTANDARD = LVCMOS33;
NET "flash_miso"      LOC="P10"  | IOSTANDARD = LVCMOS33;
#NET "flash_ext1"      LOC=""  | IOSTANDARD = LVCMOS33;
#NET "flash_ext2"      LOC=""  | IOSTANDARD = LVCMOS33;

# SD/MMC
NET "sd_cs_n"         LOC="L1"   | IOSTANDARD = LVCMOS33;
NET "sd_clk"          LOC="K1"   | IOSTANDARD = LVCMOS33;
NET "sd_mosi"         LOC="K2"   | IOSTANDARD = LVCMOS33;
NET "sd_miso"         LOC="J1"   | IOSTANDARD = LVCMOS33;

# JOYSTICK
NET "joyup"           LOC="R14"   | IOSTANDARD = LVCMOS33 | PULLUP;
NET "joydown"         LOC="T14"   | IOSTANDARD = LVCMOS33 | PULLUP;
NET "joyleft"         LOC="R15"   | IOSTANDARD = LVCMOS33 | PULLUP;
NET "joyright"        LOC="P16"   | IOSTANDARD = LVCMOS33 | PULLUP;
NET "joyfire"         LOC="P11"   | IOSTANDARD = LVCMOS33 | PULLUP;
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ZX-Uno · Clon de ordenador ZX Spectrum basado en FPGA

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brunosilva
Mensajes: 287
Registrado: 18 Jun 2016, 19:54

Re: ZX-Uno running on Next board (WIP)

Mensajepor brunosilva » 17 Dic 2017, 16:57

antoniovillena escribió:For upgrade the Next core just remove the first 512 bytes of the TBBLUE.TBU file and rename to CORE2.ZX2. Here is an utility to do this.


ups I forgot this...

v0.5 isn't yet on the site but you can get it here: https://drive.google.com/drive/folders/ ... QOMTZ1M5TN


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